{"title":"无输入级联码V/sub thn/和V/sub thp/提取电路","authors":"Yanbin Wang, G. Tarr, Yanjie Wang","doi":"10.1109/ICECS.2004.1399673","DOIUrl":null,"url":null,"abstract":"Input-free nMOS and pMOS V/sub th/ (threshold voltage) extractor circuits are presented. They use a cascode structure to eliminate the error caused by the body effect. The extracted V/sub th/ for nMOS and pMOS is referenced to ground and V/sub DD/ respectively. Both nMOS and pMOS V/sub th/ extractors have high accuracy of almost 100% from the HSPICE simulation. The nMOS and pMOS extractor circuits have been simulated in HSPICE using TSMC 0.35 /spl mu/m CMOS technology at 2 V and 2.9 V power supply with low power consumption of 0.29 mW and 0.44 mW respectively.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"44 1","pages":"282-285"},"PeriodicalIF":0.0000,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Input-free cascode V/sub thn/ and V/sub thp/ extractor circuits\",\"authors\":\"Yanbin Wang, G. Tarr, Yanjie Wang\",\"doi\":\"10.1109/ICECS.2004.1399673\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Input-free nMOS and pMOS V/sub th/ (threshold voltage) extractor circuits are presented. They use a cascode structure to eliminate the error caused by the body effect. The extracted V/sub th/ for nMOS and pMOS is referenced to ground and V/sub DD/ respectively. Both nMOS and pMOS V/sub th/ extractors have high accuracy of almost 100% from the HSPICE simulation. The nMOS and pMOS extractor circuits have been simulated in HSPICE using TSMC 0.35 /spl mu/m CMOS technology at 2 V and 2.9 V power supply with low power consumption of 0.29 mW and 0.44 mW respectively.\",\"PeriodicalId\":38467,\"journal\":{\"name\":\"Giornale di Storia Costituzionale\",\"volume\":\"44 1\",\"pages\":\"282-285\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-12-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Giornale di Storia Costituzionale\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS.2004.1399673\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"Arts and Humanities\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Giornale di Storia Costituzionale","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2004.1399673","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"Arts and Humanities","Score":null,"Total":0}
Input-free cascode V/sub thn/ and V/sub thp/ extractor circuits
Input-free nMOS and pMOS V/sub th/ (threshold voltage) extractor circuits are presented. They use a cascode structure to eliminate the error caused by the body effect. The extracted V/sub th/ for nMOS and pMOS is referenced to ground and V/sub DD/ respectively. Both nMOS and pMOS V/sub th/ extractors have high accuracy of almost 100% from the HSPICE simulation. The nMOS and pMOS extractor circuits have been simulated in HSPICE using TSMC 0.35 /spl mu/m CMOS technology at 2 V and 2.9 V power supply with low power consumption of 0.29 mW and 0.44 mW respectively.
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