Sutirtha Das, S. Mukherjee, Neha Aryani, S. Majumder, N. Bera, B. Bhattacharya
{"title":"SIMOP-A fast tool for generating optimum dilutions of microfluidic samples using simulation","authors":"Sutirtha Das, S. Mukherjee, Neha Aryani, S. Majumder, N. Bera, B. Bhattacharya","doi":"10.1109/DISCOVER.2016.7806216","DOIUrl":"https://doi.org/10.1109/DISCOVER.2016.7806216","url":null,"abstract":"The technology of digital microfluidic (DMF) biochips now offers viable replacement of expensive healthcare and bio-, chemical laboratory procedures with low-cost, fully-automated, miniaturized integrated systems. Preparing dilution of a fluid sample that optimizes various parameters such as reagent-cost, mixing time, waste production, is a basic problem in the domain of algorithmic microfluidics. Most of the existing dilution algorithms used in droplet-based microfluidic systems deploy a sequence of (1 : 1) mix-split steps, where two unit-volume droplets of different concentrations are mixed, followed by a balanced split operation to obtain two equal-sized droplets. In this paper, we introduce a simulation-guided optimization procedure (SIMOP) for achieving the target concentrations with a sequence of (1 : 1) mix-split steps while optimizing multiple factors according to user-specified priority levels. The SIMOP-algorithm produces a given concentration while optimizing each criterion as desired. Experimental results favorably demonstrate the performance of the proposed method compared to BS and DMRW algorithms. The proposed procedure may find many potential applications to microfluidics such as in' biomedical engineering and healthcare services.","PeriodicalId":383554,"journal":{"name":"2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126396738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Mukherjee, Anupam Banerjee, I. Chakrabarti, P. Dutta, A. Ray
{"title":"An efficient FPGA based implementation of forward integer transform and quantization algorithm of H.264","authors":"R. Mukherjee, Anupam Banerjee, I. Chakrabarti, P. Dutta, A. Ray","doi":"10.1109/DISCOVER.2016.7806246","DOIUrl":"https://doi.org/10.1109/DISCOVER.2016.7806246","url":null,"abstract":"Integer transformation has been used to exploit the spatial redundancy of input video in the recent video coding standard H.264. The standard has also introduced novel algorithms for quantization and inverse quantization processes. In this paper, we present efficient hardware architectures for real-time implementation of forward integer transform and quantization algorithms used in H.264 video codec. The proposed hardware architecture for forward transform is based on a reconfigurable datapath with minimum number of adders/subtractors and shifters. This hardware is designed to be used as part of a complete H.264 video coding system for realtime applications. Using Xilinx Virtex-4 technology, the proposed architecture for forward transform has been verified to run at a maximum frequency of 210 MHz.","PeriodicalId":383554,"journal":{"name":"2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125417725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Speaker verification with optimized feature subset using MOBA","authors":"J. S. Devi, S. Nandyala, P. V. B. Reddy","doi":"10.1109/DISCOVER.2016.7806242","DOIUrl":"https://doi.org/10.1109/DISCOVER.2016.7806242","url":null,"abstract":"In speech processing for speaker verification, feature subset selection is one of the key components. Feature Subset Selection (FS) also played a vital role in the fields like pattern recognition, image processing, data mining, and gene selection. In a real world problem related to speech domain, speech sample contains a large number of relevant and irrelevant features. To increase the speaker verification rate, one needs to use the optimization technique for feature selection after the feature extraction technique. The ultimate goal is to select the most relevant subset of features for error free optimized classification in the speech domain. In this regard a novel feature subset selection algorithm is proposed using Bat algorithm and Multi Objective Optimization technique. Results of the experiment shows the proposed algorithm surpassed the accuracy rates shown by the conventional systems.","PeriodicalId":383554,"journal":{"name":"2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125476396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Raghavendra, K. Nithyashree, C. Geeta, R. Buyya, K. Venugopal, S. Iyengar, L. Patnaik
{"title":"FRORSS: Fast result object retrieval using similarity search on cloud","authors":"S. Raghavendra, K. Nithyashree, C. Geeta, R. Buyya, K. Venugopal, S. Iyengar, L. Patnaik","doi":"10.1109/DISCOVER.2016.7806245","DOIUrl":"https://doi.org/10.1109/DISCOVER.2016.7806245","url":null,"abstract":"This paper involves a cloud computing environment in which the data owner out sources the similarity search service to a third party service provider. The user provides an example query to the server to retrieve similar data. Privacy of the outsourced data is important because they may be sensitive, valuable or confidential data. The data should be made available to the authorized client/client groups, but not to be revealed to the service provider in which the data is stored. Given this scenario, the paper presents a technique called FRORSS which has build phase, data transformation and search phase. The build phase is about uploading the data; the data transformation phase transforms the data before submitting it to the service provider for similarity queries on the transformed data; search phase involves searching similar object with respect to query object. Experiments have been carried out on real data sets which exhibits that the proposed work is capable of providing privacy and achieving accuracy at a lower value of result measure in comparision with FDH [1].","PeriodicalId":383554,"journal":{"name":"2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)","volume":"130 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130236134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Angshuman Khan, Sikta Mandal, Soumi Nag, R. Chakrabarty
{"title":"Efficient multiplexer design and analysis using quantum dot cellular automata","authors":"Angshuman Khan, Sikta Mandal, Soumi Nag, R. Chakrabarty","doi":"10.1109/DISCOVER.2016.7806233","DOIUrl":"https://doi.org/10.1109/DISCOVER.2016.7806233","url":null,"abstract":"Quantum dot Cellular Automata are future representations of quantum reckoning, which is developed in resemblance to the predictable models of cellular automata familiarized by Von Neumann. Quantum dot Cellular Automata (QCA) technology is striking for its low power intake, fast speed and small dimension and so it is a favorable alternative to CMOS technology. Multiplexer is an important building block of digital circuits and very useful part in most frequently used logical circuits. In this paper, a competent design of 2:1 MUX has been proposed which is smallest ever. The comparison between different existing multiplexers with the proposed one has been done successfully in this paper. There are four fabrication methodologies of QCA cell, viz. Molecular, semiconductor, magnetic, and metallic. Among all types of QCA cells, metallic one is not suitable at normal temperature. Therefore, temperature plays a key role in QCA circuit. This article includes the effect of temperature on polarization of the proposed multiplexer. Proposed design has been verified using QCA designer tool.","PeriodicalId":383554,"journal":{"name":"2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129161503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Reliable logic design with defective nano-crossbar architecture","authors":"Malay Kule, H. Rahaman, B. Bhattacharya","doi":"10.1109/DISCOVER.2016.7806231","DOIUrl":"https://doi.org/10.1109/DISCOVER.2016.7806231","url":null,"abstract":"Emerging nanoscale devices now offer viable options for replacing conventional CMOS-based designs. In this work, we study the problem of logic synthesis using nanoscale 2-D crossbar-switch architecture. Despite having several advantages, these tiny devices suffer from high defect-density because of process variations that affect their dimensions and shapes. As a result, several defective junctions often appear as spatially-clustered in nano-crossbar structures following manufacture. Additionally, the junctions that lie in the close proximity of defective ones are also prone to become faulty in the near future. Such defect-free junctions are not so reliable from the viewpoint of logic synthesis. The objective of this work is to determine a large rectangular region that is devoid of any such defects. Such a sub-crossbar region can be reliably used for mapping Boolean functions. In order to locate such regions, we use an efficient search technique based on defect geometry and report experimental results by varying crossbar-size and defect-density.","PeriodicalId":383554,"journal":{"name":"2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127936999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Mahesh D. Sawarbandhe, S. Naik, V. Satpute, S. Sinha
{"title":"Coaxial antenna for microwave ablation","authors":"Mahesh D. Sawarbandhe, S. Naik, V. Satpute, S. Sinha","doi":"10.1109/DISCOVER.2016.7806254","DOIUrl":"https://doi.org/10.1109/DISCOVER.2016.7806254","url":null,"abstract":"Microwave energy has the ability to heat the area of diseased tissue and it can be used for the local hyperthermia. Now a days hyperthermia is used to treat the cancer tumor and it is verified by several clinical trials. Depending upon the size and position of the target tumor several types of antennas are proposed by researchers. In this paper, we have designed coaxial slot antenna with operating frequency 2.45 GHz, which effectively radiates microwave energy into a target tumor. For the parameters S11, return loss, VSWR and Radiation pattern, we have simulated the design in HFSS simulator and observed the results.","PeriodicalId":383554,"journal":{"name":"2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127886298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Low cost in-pipe leak detection robot","authors":"S. Kulgod, S. Srinidhi, Satyesh Shanker Awasthi","doi":"10.1109/DISCOVER.2016.7806252","DOIUrl":"https://doi.org/10.1109/DISCOVER.2016.7806252","url":null,"abstract":"In this paper we work towards a new prototype for an inexpensive in-pipe leak detection system. Our proposed robotic system is able to detect leaks in pipes in a reliable and autonomous fashion. The robotic system inspects the network and sends leak signals wirelessly. The detection principle is based on the presence of a pressure gradient in the neighborhood of a leak in the pressurized pipe. This pressure gradient is translated into force and hence a displacement by means of a lever which comes in contact with a conducting core to produce a signal. Length and shape of the lever are changed to study the change in sensitivity.","PeriodicalId":383554,"journal":{"name":"2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121010810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"EMG controlled low cost prosthetic arm","authors":"K. Sharmila, T. Sarath, K. Ramachandran","doi":"10.1109/DISCOVER.2016.7806239","DOIUrl":"https://doi.org/10.1109/DISCOVER.2016.7806239","url":null,"abstract":"Electromyography (EMG) signals have been extensively used as a control signal in robotics, rehabilitation and health care. In this paper, cost effective design of prosthetic hand using EMG control is presented. Signal amplification and filtering is the primary step in surface EMG signal processing and application systems. Quality of the acquired EMG signal depends on the amplifiers and filters employed. Single channel continuous EMG signal has been acquired from the users arm for various hand movements. The acquired signal is passed through various stages of filters and amplifiers for amplification and noise reduction. The conditioned analog signal is converted into digital samples. After the signal acquisition process, features are extracted from the acquired signal and the extracted features are reduced to minimize the number of computations. These reduced feature parameters are used to classify the signal for different hand movements. Once the classifier identifies the intended motion, the control signal will be generated and given to the motors in the prosthetic hand to perform the intended movements. Experiments were done to find the efficiency of the developed system and it is found that this system can give basic movements at a very low cost.","PeriodicalId":383554,"journal":{"name":"2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124096603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Compiler optimization for superscalar and pipelined processors","authors":"Vishnu P. Bharadwaj, M. Rao","doi":"10.1109/DISCOVER.2016.7806224","DOIUrl":"https://doi.org/10.1109/DISCOVER.2016.7806224","url":null,"abstract":"The exploitation of parallelism at both the multiprocessor or multicore level and at the instruction level is the means to achieve high-performance. The compiler for VLIW and superscalar processors must expose sufficient parallelism to effectively utilize the parallel hardware. The amount of instruction level parallelism available to VLIW processors or superscalar processors can be limited. This will limit the performance of these processors to a certain extent. However, with compiler optimization techniques, its performance can be increased to greater extent. This evaluation shows that utilizing the existing resources of the processor with certain programmer constraints and an efficient scheduling of independent and dependent blocks of instructions, we can increase the performance of the processors. As compiler optimization interact with the micro-architecture in complex ways, certain programmer constraints can be added to reduce the complexity and help the compiler to structure the Assembly code in a manner which can be used for out-of-order execution of the code. This paper provides new methods and improvements for the structure of the Assembly code for execution on superscalar processors.","PeriodicalId":383554,"journal":{"name":"2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132617068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}