{"title":"Autocorrelation based spectrum sensing architecture on FPGA with dynamic offset compensation","authors":"P. Ishwerya, S. Geethu, G. Lakshminarayanan","doi":"10.1109/DISCOVER.2016.7806250","DOIUrl":"https://doi.org/10.1109/DISCOVER.2016.7806250","url":null,"abstract":"In this paper, FPGA implementation of an autocorrelation based spectrum detector which is capable of overcoming DC offset and frequency offset problems is presented. There exist different non-idealities which deteriorate the performance of spectrum sensing algorithms developed for cognitive radio applications. Here, we analyze the effect of DC offset, frequency offset and their combined presence on spectrum sensing performance. The compensation factors which are incorporated make the algorithm tolerant against the two offsets. Algorithmic level verification has been done on Matlab. Hardware co-simulation has been done and the system has been tested with LTE 20 MHz signals. The algorithm has been implemented on Xilinx Virtex 5 board (XC5VLX110T) and the hardware results have been validated.","PeriodicalId":383554,"journal":{"name":"2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)","volume":"34 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113984280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A power efficient phase frequency detector and low mismatch charge pump in on-chip clock generator","authors":"S. Jandhyala, Soumya Tapse","doi":"10.1109/DISCOVER.2016.7806235","DOIUrl":"https://doi.org/10.1109/DISCOVER.2016.7806235","url":null,"abstract":"In this manuscript, we propose a robust on-chip clock generator circuit using a power efficient phase frequency detector and a low current mismatch dual adaptive regulated cascode charge pump in 180nm UMC MPW RF process. The proposed PFD uses only 20 transistors and is free from dead zone. It consumes a power of 5.4μW for an input reference frequency of 50MHz and can support a maximum frequency of 2.5GHz at PLL output. The proposed charge pump limits the variation in charging and discharging currents to 0.09% of its biasing value, which is designed to be 182.5μA, for change in control voltage from 0.4V to 1.2V. This reduces the jitter to less than 2ps at the PLL output frequency of 2.3GHz. The charge pump avoids operational amplifiers in its design, resulting in lesser a rea and power without any loss in functionality.","PeriodicalId":383554,"journal":{"name":"2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116138478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Routray, M. Jha, A. Javali, Laxmi Sharma, Sutapa Sarkar, Ninikrishna T
{"title":"Software defined networking for optical networks","authors":"S. Routray, M. Jha, A. Javali, Laxmi Sharma, Sutapa Sarkar, Ninikrishna T","doi":"10.1109/DISCOVER.2016.7806260","DOIUrl":"https://doi.org/10.1109/DISCOVER.2016.7806260","url":null,"abstract":"Optical networks are evolving with the emerging advanced technologies. Their sizes and functionalities too grow with every passing year. All these complexities cannot be handled through the traditional framework for network control and management. Software defined networking (SDN) has been proposed for the control and management of networks. SDN provides several advantages for the control, operation and management of large networks. It provides flexibility and agility at every level of the network. In this paper, we present the utilities of SDN for optical networks. We also discuss the issues related to the implementation and benefits of SDN in optical networks.","PeriodicalId":383554,"journal":{"name":"2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129459868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"2-D potential model for short channel common double gate MOSFETs adapted to gate-oxide thickness symmetry","authors":"Venkata Appa Rao Yempada, S. Jandhyala","doi":"10.1109/DISCOVER.2016.7806234","DOIUrl":"https://doi.org/10.1109/DISCOVER.2016.7806234","url":null,"abstract":"Existing compact models for double gate FinFETs assume uniform gate-oxide thickness on both the functional sides of the Fins. Any difference in oxide thickness between the sides is accommodated by fit parameters in the compact model. Though such approach is sufficient in saturation regime, a more physical approach is essential to account for short-channel effects and leakage currents at weak and moderate inversions. In this manuscript, we propose a 2-D closed form surface potential model for a more generic device, the common double gate MOSFETs which can physically account for the asymmetry in thickness between the gate-oxides. The model can be used to compute body potential useful in modeling the Short channel effects, up to an oxide thickness asymmetry of 50% and up to channel lengths of 20nm.","PeriodicalId":383554,"journal":{"name":"2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122693777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
RAVISH ARADHYA H V, H. R. Madan, M. S. Suraj, Megaraj T. Mahadikar, R. Muniraj, Mohammed Moiz
{"title":"Design and performance comparison of adiabatic 8-bit multipliers","authors":"RAVISH ARADHYA H V, H. R. Madan, M. S. Suraj, Megaraj T. Mahadikar, R. Muniraj, Mohammed Moiz","doi":"10.1109/DISCOVER.2016.7806237","DOIUrl":"https://doi.org/10.1109/DISCOVER.2016.7806237","url":null,"abstract":"The advancement of transistor process technology reduces chip area at the cost of the total power consumption. Adiabatic logic, one of the promising low power techniques in VLSI gives low power dissipation at the expense of delay. In any digital hardware, the fundamental building blocks contribute to significant power dissipation and propagation delay. Multipliers are one among them which are of prime importance in Digital Signal Processing (DSP) and Image Processing applications. The present work proposes ECRL based 8-bit multiplier designs and compares them with the CMOS designs. Wallace-Dadda hybrid multiplier which uses Decomposition Logic to reduce the carry propagation delay is considered to be the reference design. 8-bit Vedic-Dadda hybrid multiplier and 8-bit Vedic multiplier are presented as power optimized designs. Hspice is used to obtain the power and delay values of the designed multipliers in CMOS and ECRL. 8-bit Vedic multiplier provides a power reduction of about 19.3% as compared to Wallace-Dadda hybrid multiplier. Overall, the proposed ECRL based multiplier dissipates about 77% less power, as compared to CMOS designs.","PeriodicalId":383554,"journal":{"name":"2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)","volume":"31 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128957607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Crowdsourcing for disaster relief: A multi-platform model","authors":"S. Murali, V. Krishnapriya, A. Thomas","doi":"10.1109/DISCOVER.2016.7806269","DOIUrl":"https://doi.org/10.1109/DISCOVER.2016.7806269","url":null,"abstract":"In this paper, we propose a model to deal with and manage disasters, taking into consideration the limitations of technology which hamper effective crisis management while handling the needs of victims, volunteers and government agencies. Our model aims at providing both an online and offline platform for data aggregation, dissemination and analysis. We propose a three level model which attempts to reduce the impact of the disaster on the victims by providing a platform that helps coordination between all parties involved, and ensures availability of resources and information. We discuss the existing solutions like Ushahidi and try to incorporate successful features into our model. Further, we use various techniques ranging from Natural Language Processing (NLP) to crowd sourcing, and ensure a robust, scalable solution which can be used by all the parties involved.","PeriodicalId":383554,"journal":{"name":"2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133218044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A comparative study of different auto-focus methods for mycobacterium tuberculosis detection from brightfield microscopic images","authors":"Gagan Saini, R. Panicker, B. Soman, Jeny Rajan","doi":"10.1109/DISCOVER.2016.7806223","DOIUrl":"https://doi.org/10.1109/DISCOVER.2016.7806223","url":null,"abstract":"Automatic tuberculosis (TB) detection methods using microscopic images are becoming more popular now a days. Auto-focusing is the first and foremost step in the development of an automated microscope for TB detection. Different focus measures exist for the selection of in-focus image from both fluorescence and bright field microscopic images. Recently, some researchers have investigated and compared several different focus measures for TB sputum microscopy. In this study we focused on bright field microscopic images and considered around 20 popular focus measures. Experiments were conducted on a large set of images having different features.","PeriodicalId":383554,"journal":{"name":"2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124182194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"System for NFC and audio multiplexing","authors":"R. R. Srinivasa, Joy Bose","doi":"10.1109/DISCOVER.2016.7806215","DOIUrl":"https://doi.org/10.1109/DISCOVER.2016.7806215","url":null,"abstract":"In this paper we present the design of a system that can seamlessly multiplex NFC signal over earphones which are meant for transmitting audio signals. The system consists of modifying the existing hardware on earphones and adding custom hardware consisting of a mixer and splitter, and making changes to the NFC antenna on mobile phones. The modifications can be made quite easily and no software changes are required. This multiplexed system lets the user to use their ear phones to make NFC transactions. Our solution is cost effective and minute enough to be implemented on a very small earphone. The hardware is designed around the fact that the NFC system filters out 13MHz so any other frequencies that are induced are filtered out, similarly the human audible range spans from 20 Hz till 20 KHz which forms a band pass filter. In our approach, the inherent nature of the system and wide spread of frequencies are leveraged to design a simple passive circuit that aims at selective impedance rather than filtering the frequencies. The hardware design ensures that the system is compatible with existing NFC applications (apps) in mobile devices. We present details of a simple proof of concept implementation of the system. We also show that different kinds of applications can be installed on a mobile phone using our system.","PeriodicalId":383554,"journal":{"name":"2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117039663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Automation of end effector guidance of robotic arm for dental implantation using computer vision","authors":"S. Yeotikar, A. M. Parimi, Y. V. Daseswar Rao","doi":"10.1109/DISCOVER.2016.7806263","DOIUrl":"https://doi.org/10.1109/DISCOVER.2016.7806263","url":null,"abstract":"Placing dental implants in humans is a task that requires a large amount of dexterity, effort and precautionary measures on behalf of the dentist. One of the most important sub-task of this procedure is drilling a hole in the jaw of patient. Increasing advances in the field of robotics have made it possible to build robotic arms that can attain the same degree of precision as that of dentist for this sub-task, thus opening a possibility of automating the entire process which would save time and effort of dentists. In addition, vision equips a robot with a large amount of information like the objects in surroundings, their shape, color, etc. This information on being processed can be used to perform actions by a robot to interact with the surroundings and accomplish a certain goal. In this paper, one such application of computer vision has been discussed to accomplish the goal of automation of end effector guidance for dental implantation in human mandible by means of a robotic arm. Computer vision has been used to establish a closed loop feedback control system for the robotic arm, so as to make the end effector of robotic arm reach the desired location for drilling the hole in jaw. Template matching is used to detect the desired point in subsequent frames captured by a camera mounted at the end effector also consisting of a drilling machine. The system proposed in this paper reliably establishes complete automation of the process, thus demanding only a mouse click effort from the dentist.","PeriodicalId":383554,"journal":{"name":"2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115583521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A survey on replacement strategies in cache memory for embedded systems","authors":"Parag Panda, Geeta Patil, B. Raveendran","doi":"10.1109/DISCOVER.2016.7806218","DOIUrl":"https://doi.org/10.1109/DISCOVER.2016.7806218","url":null,"abstract":"Cache is one of the most power-consuming components in computer architecture. Power reduction in cache can be achieved by reducing miss rate miss penalty latency per access and power consumption per access. The power reduction can also be achieved by shutting down unused part of the cache by allowing not so recently used cache banks to sleep reconfiguring the cache for specific application and various combinations of one or more of these. The cache hit depends on the cache size associativity and the cache line size. Replacement strategies in associative mapping schemes play an important role in cache hit rate performance. This survey paper proposes a classification of these strategies with detailed discussion on their advantages and disadvantages.","PeriodicalId":383554,"journal":{"name":"2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114552129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}