An efficient FPGA based implementation of forward integer transform and quantization algorithm of H.264

Abstract

Integer transformation has been used to exploit the spatial redundancy of input video in the recent video coding standard H.264. The standard has also introduced novel algorithms for quantization and inverse quantization processes. In this paper, we present efficient hardware architectures for real-time implementation of forward integer transform and quantization algorithms used in H.264 video codec. The proposed hardware architecture for forward transform is based on a reconfigurable datapath with minimum number of adders/subtractors and shifters. This hardware is designed to be used as part of a complete H.264 video coding system for realtime applications. Using Xilinx Virtex-4 technology, the proposed architecture for forward transform has been verified to run at a maximum frequency of 210 MHz.