Lithography Asia最新文献_第9页

Overlay improvement by ASML HOWA 5th alignment strategy ASML HOWA第五对齐策略的覆盖改进

Lithography Asia Pub Date : 2009-12-03 DOI: 10.1117/12.839816

R. Wang, Cy Chiang, W. Hsu, Richer Yang, Todd T. Shih, Jackie H. Chen, J.F. Chiu, W. Lin

{"title":"Overlay improvement by ASML HOWA 5th alignment strategy","authors":"R. Wang, Cy Chiang, W. Hsu, Richer Yang, Todd T. Shih, Jackie H. Chen, J.F. Chiu, W. Lin","doi":"10.1117/12.839816","DOIUrl":"https://doi.org/10.1117/12.839816","url":null,"abstract":"Overlay control is more challenging when DRAM volume production continues to shrink its critical dimention (CD) to 70nm and beyond. Effected by process, the overlay behavior at wafer edge is quite different from wafer center. The big contribution to worse overlay at wafer edge which causes yield loss is misalignment. The analysis in wafer edge suggests that high order uncorrectable overlay residuals are often observed by certain process impact. Therefore, the basic linear model used for alignment correction is not sufficient and it is necessary to introduce an advanced alignment correction model for wafer edge overlay improvement. In this study, we demonstrated the achievement of moderating the poor overlay at wafer edge area by using a high order wafer alignment strategy. The mechanism is to use non-linear correction methods of high order models ( up to 5th order), with support by the function High Order Wafer Alignment (known as HOWA) in scanner. Instead of linear model for the 6 overlay parameters which come from average result, HOWA alignment strategy can do high order fitting through the wafer to get more accurate overlay parameters which represent the local wafer grid distortion better. As a result, the overlay improvement for wafer edge is achieved. Since alignment is a wafer dependent correction, with HOWA the wafer to wafer overlay variation can be improved dynamically as well. In addition, the effects of different mark quantity and sampling distribution from HOWA are also introduced in this paper. The results of this study indicate that HOWA can reduce uncorrectable overlay residual by 30~40% and improve wafer-to-wafer overlay variation significantly. We conclude that HOWA is a noteworthy strategy for overlay improvement. Moreover, optimized alignment mark numbers and distribution layout are also key factors to make HOWA successful.","PeriodicalId":383504,"journal":{"name":"Lithography Asia","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127037714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Expanding the lithography process window (PW) with CDC technology 用CDC技术扩展光刻工艺窗口(PW

Lithography Asia Pub Date : 2009-10-01 DOI: 10.1117/12.845618

Sz-Huei Wang, G. Ben-Zvi, Yu-Wan Chen, C. Kuo, Erez Graitzer, Avi Cohen

{"title":"Expanding the lithography process window (PW) with CDC technology","authors":"Sz-Huei Wang, G. Ben-Zvi, Yu-Wan Chen, C. Kuo, Erez Graitzer, Avi Cohen","doi":"10.1117/12.845618","DOIUrl":"https://doi.org/10.1117/12.845618","url":null,"abstract":"The continuous shrinking of the semiconductor device nodes requires tough specifications of CD uniformity which result in narrowing of the lithography process window. Finding methods for expanding the process window will enable to continue manufacturing at least one more generation using the existing litho equipment. The CDC technology has been described in detail in past studies beginning in 2006; however it has typically been studied from a mask shop perspective. In this paper we will demonstrate a way to improve the CD Uniformity (CDU) on a new mask, which has a CD uniformity problem that leads to shrinking of the lithography process window, by using the Carl Zeiss CD Control (CDC) Technology. The methodology used and the process window improvement verification we show are based purely on fab available techniques and do not require any input from the mask shop. A production memory product in PSC fab P1/2 showed reduced yield due to reduced process window in one line/space (L/S) layer. A close investigation in the fab showed wafer CD non-uniformity of 6.5nm Range and 3.95nm 3S in this layer due to a mask CDU problem. A CDC process to improve the CDU was applied by the Carl Zeiss CDC200 tool based on wafer CD data only. Post CDC treatment results show that CD Range was reduced to 3.8nm (42% improvement) and 3S was reduced to 1.94nm (51% improvement). Further assessment of the litho process window of this layer showed an increase of CD-DOF from 0.15um before (Pre) CDC to 0.30um after (Post) CDC and an exposure latitude increase from 14.1% Pre to 26.7% Post CDC. To summarize our findings, applying the CDC process to the problematic layers allowed to increase the PW in both DOF and exposure latitude by improving the CDU of the layer. This resulted in better yield of this product.","PeriodicalId":383504,"journal":{"name":"Lithography Asia","volume":"7520 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129854717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Bottom anti-reflective coating for hyper NA process: theory, application and material development 超NA工艺底防反射涂层:理论、应用及材料开发

Lithography Asia Pub Date : 2008-12-04 DOI: 10.1117/12.804617

H. Yao, JoonYeon Cho, Jian Yin, S. Mullen, Guanyang Lin, M. Neisser, R. Dammel

引用次数: 1

A new calibration method for latent image fidelity 一种新的潜在图像保真度校正方法

Lithography Asia Pub Date : 2008-12-04 DOI: 10.1117/12.804271

E. Barouch, Stephen L. Knodle

{"title":"A new calibration method for latent image fidelity","authors":"E. Barouch, Stephen L. Knodle","doi":"10.1117/12.804271","DOIUrl":"https://doi.org/10.1117/12.804271","url":null,"abstract":"With the shrinking of all fundamental features in modern IC manufacturing, the aerial image calculation is becoming insufficient for accurate simulation of the printable wafer. In this presentation, a reliable simulation methodology based on basic principles is being introduced which includes an exact analytical solution of the Maxwell equations inside the photoresist as well as all other relevant layers. This solution contains multi-layers including bottom anti-reflection coating (BARC), silicon dioxide, nitride layers, as well as immersion in the medium between the stepper and the photoresist. The calibration is performed in order of parameter importance. This calibration gives higher weight to the most critical parameters. The latent image in the resist is computed, the resulting acid concentration is derived from the latent image, and the PEB (post exposure baking) is completed by invoking a reaction-diffusion system. The diffusion equation component orthogonal to the resist surface is solved exactly in closed form due to the small dimension of the resist thickness. The development is performed in a similar way. The latent image is compared to SEM images and the simulation parameters are calibrated through a newly developed optimization scheme to produce very accurate simulation fidelity. The methodology given here has been very successfully applied in detection of printing failures (hot-spots) for state of the art compact designs. An accuracy smaller than 1nm has been obtained. The system is very fast, suitable for entire chip analysis and highly parallelized. This calibration can be performed on a dual core laptop. Several practical examples are given.","PeriodicalId":383504,"journal":{"name":"Lithography Asia","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120990867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Development of multi-layer process materials for hyper-NA lithography process 超na光刻多层工艺材料的研制

Lithography Asia Pub Date : 2008-12-04 DOI: 10.1117/12.804688

Yasushi Sakaida, M. Nakajima, Tetsuya Shinjo, Keisuke Hashimoto

{"title":"Development of multi-layer process materials for hyper-NA lithography process","authors":"Yasushi Sakaida, M. Nakajima, Tetsuya Shinjo, Keisuke Hashimoto","doi":"10.1117/12.804688","DOIUrl":"https://doi.org/10.1117/12.804688","url":null,"abstract":"In order to achieve miniaturization of the device, and still following device design rules, the photo-resist film thickness has decreased. The thinner photo-resist thickness will improve the resolution limit and prevent the pattern collapse issue. In order to solve these problems a multilayer process is used that has several advantages over previous process designs: reflectivity control in hyper-NA lithography process, decreasing LWR, and the viewpoint of lithographic process margin. The multilayer process consists of three layers: layer one is patterned photo-resist, the second layer is Si-ARC (Si contented Anti Reflective Coatings), and the third layer is SOC (Spin on Carbon) also known as underlayer. There are two processes to deposit Si-ARC and SOC, the first is by spin coating with either a track or spin coater, the second is with a Chemical Vapor Deposition (CVD). From a cost of ownership standpoint the spin on process is better. In the development of spin on Si-ARC and SOC materials it is important to consider the resist profile and the shelf life stabilities. Another important attribute to consider is the etching characteristics of the material. For the Si-ARC the main attribute when determining etch rate is the Si content and for the SOC material the main attribute is the C content in the material. One problem with the spin on multilayer process is resist profile and this paper will examine this problem along with the characteristics of developed material is described.","PeriodicalId":383504,"journal":{"name":"Lithography Asia","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133716164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Mask specification guidelines in spacer patterning technology 间隔图案技术中的掩模规范指南

Lithography Asia Pub Date : 2008-12-04 DOI: 10.1117/12.804744

K. Hashimoto, H. Mukai, S. Miyoshi, S. Yamaguchi, H. Mashita, Y. Kobayashi, K. Kawano, T. Hirano

引用次数: 0

High Si content BARC for applications in dual BARC systems such as tri-layer patterning 高硅含量BARC用于双BARC系统，如三层图案

Lithography Asia Pub Date : 2008-12-04 DOI: 10.1117/12.804699

Joseph T. Kennedy, Songyuan Xie, Ze Wu, R. Katsanes, Kyle Flanigan, Kevin J. Lee, M. Slezak, N. Fender, J. Takahashi

{"title":"High Si content BARC for applications in dual BARC systems such as tri-layer patterning","authors":"Joseph T. Kennedy, Songyuan Xie, Ze Wu, R. Katsanes, Kyle Flanigan, Kevin J. Lee, M. Slezak, N. Fender, J. Takahashi","doi":"10.1117/12.804699","DOIUrl":"https://doi.org/10.1117/12.804699","url":null,"abstract":"This work discusses the requirements and performance of Honeywell's middle layer material, UVAS, for trilayer patterning. UVAS is a high Si content polymer synthesized directly from Si containing starting monomer components. The monomers are selected to produce a film that meets the requirements as a middle layer for trilayer patterning and gives us a level of flexibility to adjust the properties of the film to meet the customer's specific photoresist and patterning requirements. Results of simulations of the substrate reflectance versus numerical aperture, UVAS thickness, and under layer film are presented. Immersion lithographic patterning of ArF photoresist line space and contact hole features will be presented. A sequence of SEM images detailing the plasma etch transfer of line space photoresist features through the middle and under layer films comprising the TLP film stack will presented. Excellent etch selectivity between the UVAS and the organic under layer film exists as no edge erosion or faceting is observed as a result of the etch process. The results of simulations of Rsub versus NA, and the thickness of each film comprising a two layer antireflective film stack will also be discussed.","PeriodicalId":383504,"journal":{"name":"Lithography Asia","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123126070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Analysis of the effect of laser bandwidth on imaging of memory patterns 激光带宽对记忆图形成像的影响分析

Lithography Asia Pub Date : 2008-12-04 DOI: 10.1117/12.804557

N. Seong, Insung Kim, Dongwoo Kang, Sang-ho Lee, Ji-Hyeun Choi

{"title":"Analysis of the effect of laser bandwidth on imaging of memory patterns","authors":"N. Seong, Insung Kim, Dongwoo Kang, Sang-ho Lee, Ji-Hyeun Choi","doi":"10.1117/12.804557","DOIUrl":"https://doi.org/10.1117/12.804557","url":null,"abstract":"Tighter CD control requirements of the smaller devices in modern semiconductor products demand control of all potential sources of change in imaging characteristics. Bandwidth of ArF lasers is known to be one of the important parameters to be controlled to improve CD control of wafers. CD changes of Device Critical Patterns for memory products, for example spacing of DRAM isolation patterns, due to laser bandwidth changes were investigated through simulations. The purpose of the simulation study was to find out if there are optimum combinations of layout and illumination setting, if variations can be compensated by illumination adjustments and if the bandwidth performance of the laser meets requirements. The simulations were carried out using Cymer proprietary methods for high accuracy using improved laser spectrum sampling techniques[1]. Different CD behavior was observed for different combinations of pattern layout, illumination and bandwidth. Preferred illumination settings were found which suppress CD changes caused by bandwidth variation, especially for diffusion layer of DRAM layouts. Adjustment of illumination settings was demonstrated to cancel out CD shifts due to bandwidth change for the diffusion layer case. For all example cases, which demonstrated typical DRAM product conditions, simulation verified that the amount of CD shift can be controlled within allowed tolerances if Cymer's ABS technology was used for bandwidth control.","PeriodicalId":383504,"journal":{"name":"Lithography Asia","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131954623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Acid diffusion length dependency for 32-nm node attenuated and chromeless phase shift mask 32 nm节点衰减无铬相移掩模的酸扩散长度依赖性

Lithography Asia Pub Date : 2008-12-04 DOI: 10.1117/12.804611

Jee-Hye You, Young-Min Kang, Mi-Rim Jung, Hye-keun Oh

引用次数: 1

Robust mask design with defocus variation using inverse synthesis 利用逆合成法设计具有离焦变化的鲁棒掩模

Lithography Asia Pub Date : 2008-12-04 DOI: 10.1117/12.804681

N. Jia, A. Wong, E. Lam

引用次数: 40