{"title":"In-situ monitoring and control of photoresist parameters during thermal processing in the lithography sequence","authors":"Xiaodong Wu, Geng Yang, Ee-Xuan Lim, A. Tay","doi":"10.1117/12.847879","DOIUrl":"https://doi.org/10.1117/12.847879","url":null,"abstract":"The rapid transition to smaller microelectronic feature sizes involves the introduction of new lithography technologies, new photoresist materials, and tighter processes specifications. This transition has become increasingly difficult and costly. The application of advanced computational and control methodologies have seen increasing utilization in recent years to improve yields, throughput, and, in some cases, to enable the actual process to print smaller devices. In this work, we demonstrate recent advances in real-time monitoring and control of these photoresist parameters with the use of innovative technologies, control and signal processing techniques; and integrated metrology to improve the performance of the various photoresist processing steps in the lithography sequence.","PeriodicalId":383504,"journal":{"name":"Lithography Asia","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134080055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Analyzing electrostatic induced damage risk to reticles with an in situ e-reticle system","authors":"R. Tu, T. Sebald","doi":"10.1117/12.837039","DOIUrl":"https://doi.org/10.1117/12.837039","url":null,"abstract":"E-Reticle™ system is an electrostatic field test device, which has the form factor of a conventional six inch quartz production reticle. The E-Reticle was used to assess the ESD damage risks in a mask cleaning tool. Test results indicate that a reticle may see higher than ITRS recommended electrostatic potential specifications when mechanical operations and cold DIW rinse start and in progress, hence seeing increased probability of electrostatic induced damages.","PeriodicalId":383504,"journal":{"name":"Lithography Asia","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123279469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Control of CD errors and hotspots by using a design based verification system","authors":"Bong-Seok Choi, Sang-ho Lee, Y. Kang, W. Han","doi":"10.1117/12.839644","DOIUrl":"https://doi.org/10.1117/12.839644","url":null,"abstract":"The shrink of device node to raise the integration is important for the raising of cost performance on memory device. Targeting the feature critical dimension (CD) and defect control to achieve a large process margin and high product yield become an essential management point under the node shrink, thus sufficient works have been progressed on the product level. In the immersion lithography, the performance of CD and defect control range is intensively improved because of high equipment performances. However, proximity effect causes the CD variation and unknown hotspots because of environmental variation. In this work, control of the CD errors and hotspots will be discussed by using a verification system with an image verifier algorithm between design layout and wafer images. We used NGR2100TM as a verification system. The verification works for the CD distributions and hotspot detection are implemented on sub 50 nm node memory device. In the experiment, improved CD distributions were examined based on retarget correction for CD errors and the controllability of hotspots are explained from the examined methodology.","PeriodicalId":383504,"journal":{"name":"Lithography Asia","volume":"408 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116691072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Abdallah, K. Kurosawa, E. Wolfer, V. Monreal, M. Dalil Rahman, Dongkwan Lee, M. Neisser, R. Dammel
{"title":"Image reversal trilayer materials and processing","authors":"D. Abdallah, K. Kurosawa, E. Wolfer, V. Monreal, M. Dalil Rahman, Dongkwan Lee, M. Neisser, R. Dammel","doi":"10.1117/12.837017","DOIUrl":"https://doi.org/10.1117/12.837017","url":null,"abstract":"Image reversal trilayer (IRT) combines three lithographic patterning enhancement approaches: image reversal, spin on hard masks, and shrink for recess types of features. With IRT, photoresist imaging is done directly on top of the carbon underlayer. Thick IRT-Carbon Hard Masks (CHM) films provide effective antireflection with high NA lithography and are more etch resistant than common photoresist. IRT-Silicon Hard Masks (SiHM) can be coated over the resist patterns in the lithography track. IRT etching reverses the resist pattern into the IRT-SiHM and transfers this image to the IRTCHM. The recessed patterns in the IRT-CHM are smaller than the CD of the photoresist feature from an inherent shrinking capability of the IRT-SiHM. Continuous improvements to both IRT-SiHM and IRT-CHM have been made. Silicon contents in IRT-SiHM have been pushed as high as possible while not impacting other important properties such as stability, coating quality and resist compatibility. Newer polysiloxane IRT-SiHM no longer require resist freezing prior to coating. Carbon contents in IRTCHM have been pushed as high as possible while maintaining solubility and a low absorption which is important when resist imaging is done directly on top of the IRT-CHM. Feasibility of this image reversal trilayer process was previously demonstrated on L/S and pillar gratings. Recent work focused on nonsymmetrical 2D gratings and simultaneous patterning of L/S gratings at different pattern densities. Particular emphasis is given to pattern density effects which are applicable to any top-coating image reversal process. This paper describes the lithography, pattern transfer process and 2nd generation hard mask materials developed for IRT processing.","PeriodicalId":383504,"journal":{"name":"Lithography Asia","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134595129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Seongbo Shim, Young-chang Kim, S. Jang, Hee-bom Kim, Sung-woo Lee, Seong-woon Choi, Han-ku Cho, Chan-hoon Park
{"title":"Development and evaluation of new MRC parameter for aggressive mask optimization","authors":"Seongbo Shim, Young-chang Kim, S. Jang, Hee-bom Kim, Sung-woo Lee, Seong-woon Choi, Han-ku Cho, Chan-hoon Park","doi":"10.1117/12.839398","DOIUrl":"https://doi.org/10.1117/12.839398","url":null,"abstract":"As the design node gets smaller, using the aggressive mask optimization becomes indispensable emerging technology. However, during the aggressive optimization, we have frequently met problems that the optimized feature size gets smaller as Mask manufacturing Rule Checking (MRC) limitation. In this case, process window cannot improve more. Moreover, mask drawing error could be significant when the optimized main feature is as small as MRC limitation. As a solution for this problem, we have generally tried to develop the advanced mask manufacturing process. However, nowadays, it is truly not easy to improve the mask resolution. In this study, we found out the fact that the current MRC parameters are not good enough to reflect the mask patterning limitation. Thus, many small patterns have been eliminated by the MRC during the optimization, even though the patterns could be drawn well on the mask. In this paper, we suggest more effective MRC parameter; area based MRC. We introduce the evaluation result that represents the actual coverage of MRC. It proves that the area based MRC can reflect the mask process limitation much better than current MRC. Finally it is shown that the effect and utility of the area based MRC on the practical case by using inverse lithography technology (ILT).","PeriodicalId":383504,"journal":{"name":"Lithography Asia","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134431188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Hsu, Zhipan Li, Luoqi Chen, K. Gronlund, Hua‐yu Liu, R. Socha
{"title":"Source-mask co-optimization: optimize design for imaging and impact of source complexity on lithography performance","authors":"S. Hsu, Zhipan Li, Luoqi Chen, K. Gronlund, Hua‐yu Liu, R. Socha","doi":"10.1117/12.838701","DOIUrl":"https://doi.org/10.1117/12.838701","url":null,"abstract":"The co-optimization of the source and mask patterns [1, 2] is vital to future advanced ArF technology node development. This paper extends work previously reported on this topic [3, 4]. We will systematically study the impact of source on designs with different k1 values using SMO. Previous work compared the co-optimized versus iterative source-mask optimization methods [3]. We showed that the co-optimization method clearly improved lithography performance. This paper's approach consists of: 1) Co-optimize a pixelated freeform source and a continuous transmission gray tone mask based on a user specified cost function; 2) ASML-certified scanner-specific models and constraints are applied to the optimized source; 3) Assist feature (AF) \"seeds\" are identified from the optimized continuous transmission mask (CTM). Both the AF seed and the main feature are subsequently converted into a polygon mask; 4) The extracted AF seeds and main features are co-optimized with the source to achieve the best lithographic performance. Using this approach, we first use a DRAM brick wall design to demonstrate that using the same cost function metric by adjusting the optimization conditions creates an image log slope only optimization that can easily be applied. An optimize design for imaging methodology is introduced and shown to be important for low k1 imaging. A typical 2x node SRAM design is used to illustrate an integrated SMO design rule optimization flow. We use the same SRAM layout that used design rule optimization to study the source complexity impact with a range of k1 values that varies from 0.42 to 0.35. For the source type, we use freeform and traditional finite pole shape DOEs, all subject to ASML's scanner-specific models and constraints. We report the process window, MEF and process variation band (PV band) with different source types to find which source type give the best lithography performance.","PeriodicalId":383504,"journal":{"name":"Lithography Asia","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131399029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
James Moon, Cheol-kyun Kim, Byoung-sub Nam, Byong-Ho Nam, Chang-moon Lim, D. Yim, Sung-ki Park
{"title":"Comparison of simulation and wafer results for shadowing and flare effect on EUV alpha demo tool","authors":"James Moon, Cheol-kyun Kim, Byoung-sub Nam, Byong-Ho Nam, Chang-moon Lim, D. Yim, Sung-ki Park","doi":"10.1117/12.837136","DOIUrl":"https://doi.org/10.1117/12.837136","url":null,"abstract":"In this study, in order to accurately predict the shadowing and flare effect of EUVL, we compared and analyzed the wafer and simulation result of the shadowing and flare effect of the EUV alpha demo tool at IMEC. Flare distribution of the EUV Alpha Demo tool was measured and was used in simulation tool to simulate several test case wafer result. Also, shadowing effect of the in-house created mask was measured and compared with simulation result to match the predictability of the simulation tool. Shadowing test comparison of wafer to simulation showed that simulation with resist model showing better overall fitness to actual wafer result. Both aerial and resist model simulation result was within 2.33nm to wafer result. Measured wafer CD to simulation CD comparison for flare showed that average error RMS of 3 test cases was 0.52, 2.05 and 3.47 nm for each test case respectively. In order to have higher accuracy for flare simulation, larger diameter size for flare profile is necessary. Also from shadow test, resist model better fit the wafer trend than using only the aerial image for simulating shadowing effect. EUV tool showed very promising result for sub 30nm DRAM critical layer printing ability and with proper flare and shadowing correction, reasonable result is expected for sub 30 and beyond critical layers of DRAM using EUV lithography. Further work will be done to compensate flare and shadowing effect of EUV.","PeriodicalId":383504,"journal":{"name":"Lithography Asia","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116260484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Novel assist feature design to improve depth of focus in low k1 EUV lithography","authors":"Hoyoung Kang","doi":"10.1117/12.849556","DOIUrl":"https://doi.org/10.1117/12.849556","url":null,"abstract":"With the expected continual progress of micro-electronics scaling, low k1 techniques may be required even with EUV lithography. One of important techniques of low k1, the off axis illumination (OAI) in combination with sub-resolution assist features (SRAF) on reticles, has been used extensively in optical lithography. Use of assist features combined with off axis illumination typically requires extremely small pattern sizes. The assist pattern enables printing dense and isolated lines simultaneous. In a low k1 region of around 0.4, assist features will increase depth of focus (DOF) of isolated and semi-isolated lines even in EUV. Since EUVL process operates at a relatively higher k1 value than that for the optical lithography, the assist feature size needed is relatively smaller. In addition, with the mask shadowing effect of EUVL, all horizontal lines should be biased thinner by a couple of nanometers, and horizontal assist features will need to do the same. Fabricating such narrow features on masks is challenging, and could potentially limit the application of SRAF in EUVL in the low k1 regime. A novel approach is proposed to create assist features with similar width as the main critical dimension features. The proposed technique creates assist patterns using thinner absorber which would have higher reflectance than normal absorber. Thinner absorber assist pattern can perform similarly with narrower assist pattern and easier to fabricate. With off axis illumination in EUVL and assist patterns, process margin of semi-isolated and isolated lines can be increased for k1 lower than 0.4.","PeriodicalId":383504,"journal":{"name":"Lithography Asia","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122176623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Shimomura, Yuichi Inazuki, Abe Tsukasa, T. Takikawa, Yasutaka Morikawa, H. Mohri, N. Hayashi, Fei Wang, Long Ma, Yan Zhao, Chiyan Kuan, Hong Xiao, J. Jau
{"title":"EUV mask pattern inspection with an advanced electron beam inspection system","authors":"T. Shimomura, Yuichi Inazuki, Abe Tsukasa, T. Takikawa, Yasutaka Morikawa, H. Mohri, N. Hayashi, Fei Wang, Long Ma, Yan Zhao, Chiyan Kuan, Hong Xiao, J. Jau","doi":"10.1117/12.837025","DOIUrl":"https://doi.org/10.1117/12.837025","url":null,"abstract":"Readiness of defect-free mask is one of the biggest challenges to insert extreme ultraviolet (EUV) lithography into semiconductor high volume manufacturing for 22nm half pitch (HP) node and beyond. According to ITRS roadmap updated in 2008, minimum size of defect needed to be removed is 25nm for 22nm HP node in 2013 [1]. It is necessary, therefore, to develop EUV mask pattern inspection tool being capable of detecting 25nm defect. Electron beam inspection (EBI) is one of promising tools which will be able to meet such a tight defect requirement. In this paper, we evaluated defect detection sensitivity of electron beam inspection (EBI) system developed by Hermes Microvision, Inc. (HMI) using 88nm half-pitch (HP) line-and-space (L/S) pattern and 128nm HP contact-hole (C/H) pattern EUV mask. We found the EBI system can detect 25nm defects. We, furthermore, fabricated 4 types of EUV mask structures: 1) w/ anti-reflective (AR) layer and w/ buffer layer, 2) w/ AR layer and w/o buffer layer, 3) w/o AR layer and w/ buffer layer, 4) w/o AR layer and w/o buffer layer. And the sensitivity and inspectability for the EBI were compared. It was observed that w/o AR layer structure introduce higher image contrast and lead to better inspectability, although there is no significant different in sensitivity.","PeriodicalId":383504,"journal":{"name":"Lithography Asia","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132456959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Back side photomask haze revisited","authors":"B. Grenon, O. Kishkovich","doi":"10.1117/12.840273","DOIUrl":"https://doi.org/10.1117/12.840273","url":null,"abstract":"Back (glass) side haze on photomasks has been previously reported and continues to present problems in many fabs throughout the industry. While some process changes have resulted in the reduction in both the occurrences and rate at which back side haze forms; proper handling and storage of reticles remains paramount in protecting all surfaces on the reticle from haze formation. We will describe again the basic mechanisms for haze formation and how proper storage can result in significantly reducing the risk of haze formation during storage and use in the fab.","PeriodicalId":383504,"journal":{"name":"Lithography Asia","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126464331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}