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A drain current based short circuit protection technique for SiC MOSFET 基于漏极电流的SiC MOSFET短路保护技术
2018 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2018-03-01 DOI: 10.1109/ISDCS.2018.8379649
Yash Sukhatme, M. Krishna, P. Ganesan, K. Hatua
{"title":"A drain current based short circuit protection technique for SiC MOSFET","authors":"Yash Sukhatme, M. Krishna, P. Ganesan, K. Hatua","doi":"10.1109/ISDCS.2018.8379649","DOIUrl":"https://doi.org/10.1109/ISDCS.2018.8379649","url":null,"abstract":"SiC MOSFETs based power converters are an attractive alternative to IGBTs due to the reduced size and weight of the converter. However, as the leakage inductance is very small it causes a rapid rise in device current under short circuit conditions. As a result, SiC MOSFET cannot withstand short circuit faults for durations as long as the IGBT, thus, the reliability of SiC MOSFET can be a hindrance to it's widespread adoption. This paper analyzes the shortcomings of the present short circuit protection techniques which are presented in literature. Further, a practical short circuit protection technique for SiC MOSFETs by sensing the drain current id from the device di/dt has been presented in the paper. The proposed method eliminates the delays in the present short circuit protection methods and can detect Hard Switching Fault (HSF) and Fault Under Load (FUL) as well.","PeriodicalId":374239,"journal":{"name":"2018 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131859816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A comparative study of above- and sub-threshold characteristics of strained and unstrained Si GAA MOSFETs 应变和非应变Si GAA mosfet的阈值以上和亚阈值特性比较研究
2018 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2018-03-01 DOI: 10.1109/ISDCS.2018.8379655
T. Sharma, Subindu Kumar
{"title":"A comparative study of above- and sub-threshold characteristics of strained and unstrained Si GAA MOSFETs","authors":"T. Sharma, Subindu Kumar","doi":"10.1109/ISDCS.2018.8379655","DOIUrl":"https://doi.org/10.1109/ISDCS.2018.8379655","url":null,"abstract":"Gate-all-around (GAA) architectures are the most promising and demanding structures among all multi-gate metal-oxide semiconductor field-effect transistors (MOSFETs). With incorporation of strained-Silicon (S-Si) and multi-channel (MC) configuration, the performance of such devices can be boosted up further to several folds. However, the presence of source (S) and drain (D) series resistance in the intrinsic device may alter the performance parameters of such devices, particularly in the nanometer and deep-nanometer regime. Furthermore, the ideal circular GAA device cross-section cannot be guaranteed after fabrication due to process limitations. One of the possibilities is that the frozen S-Si GAA devices may bear elliptical cross-section with different minor and major axes, variation of which may alter the effective diameter of then device. This paper is an effort to present a comprehensive analysis of unstrained and S-Si GAA MOSFET performance in the above- and sub-threshold region, taking into account these non-ideal effects. We have also proposed an analytical expression of sub-threshold current of biaxial S-Si GAA device, which may be helpful in the current 7 nm Technology Node.","PeriodicalId":374239,"journal":{"name":"2018 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128799716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Investigation of surface potential for double gate hetero junction tunnel FinFET: Application to high-& material HfO2 双栅异质结隧道FinFET表面电位的研究:在高材料HfO2上的应用
2018 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2018-03-01 DOI: 10.1109/ISDCS.2018.8379663
Brahmdutta Dixit, N. P. Maitya, A. Dikshit, S. Tiwari, Ankush, J. Rana, Vijaya Kumar
{"title":"Investigation of surface potential for double gate hetero junction tunnel FinFET: Application to high-& material HfO2","authors":"Brahmdutta Dixit, N. P. Maitya, A. Dikshit, S. Tiwari, Ankush, J. Rana, Vijaya Kumar","doi":"10.1109/ISDCS.2018.8379663","DOIUrl":"https://doi.org/10.1109/ISDCS.2018.8379663","url":null,"abstract":"Tunnel FETs (TFETs) shown to be the promising devices for low standby power applications but suffers from low ON and high threshold voltage. The hetero junction tunnel FinFET has been studied here to overcome these limitations. In this work, surface potential has been modeled for double gate hetero junction tunnel FinFET to optimize the performance. Surface potential derived by applying the solution of 2-D Poisson equation and it is developed using superposition technique. The high-& dielectric material HfO2 on the surface potential model is also addressed. The analytical predictions are compared with the results obtained by the 2-D numerical techniques and Technology Computer Aided Design (TCAD) simulator (Synopsys TCAD), the obtained results are almost similar.","PeriodicalId":374239,"journal":{"name":"2018 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114253924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Performance evaluation of double gate III-V heterojunction tunnel FETs with SiO2/HfO2 Gate oxide structure SiO2/HfO2氧化栅结构双栅III-V异质结隧道场效应管的性能评价
2018 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2018-03-01 DOI: 10.1109/ISDCS.2018.8379681
Sanjay Kumar, K. Baral, S. Chander, P. Singh, Balraj Singh, S. Jit
{"title":"Performance evaluation of double gate III-V heterojunction tunnel FETs with SiO2/HfO2 Gate oxide structure","authors":"Sanjay Kumar, K. Baral, S. Chander, P. Singh, Balraj Singh, S. Jit","doi":"10.1109/ISDCS.2018.8379681","DOIUrl":"https://doi.org/10.1109/ISDCS.2018.8379681","url":null,"abstract":"In this work, we present a 2-D numerical simulation based study for the performance evaluation in terms of drain current, total capacitance, cut-off frequency, transconductance generation factor and transit time of double-gate (DG) heterojunction tunnel field effect transistors (HJ-TFETs) with SiO2/HfO2 stacked gate oxide structure. We also demonstrated that the proposed device shows better results in terms of subthreshold swing (SS=1.5mV/dec) and Ion/Ioff ratio (1e12) than other conventional homo/hetero junction TFET devices. All the simulation plots are obtained by 2-D simulation software ATLAS™ from SILVACO international.","PeriodicalId":374239,"journal":{"name":"2018 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131117157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Speech controlled 3D robot to arrange things 语音控制的3D机器人来整理东西
2018 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2018-03-01 DOI: 10.1109/ISDCS.2018.8379665
Madhu Singh, Amrutha Reddy Konala
{"title":"Speech controlled 3D robot to arrange things","authors":"Madhu Singh, Amrutha Reddy Konala","doi":"10.1109/ISDCS.2018.8379665","DOIUrl":"https://doi.org/10.1109/ISDCS.2018.8379665","url":null,"abstract":"In this paper a speech-controlled 3D robot to arrange things is proposed. Speech controlled robot is much easy to work with and user friendly than automatic robots and remote-controlled robots. The proposed robot has three subsystems. They are :3D scanning Sub-system, movement subsystem which includes the lifting mechanism and Speech recognition sub-system. In this work, the initial scanning is done by time of flight laser range finder then Surface reconstruction is done from the point cloud data obtained through scanning by Poisson surface reconstruction technique. Thus, pictorial view of room is obtained, next training of HM2007 IC (speech IC) is to be performed to follow our commands and finally the orientation and joint angles for a required position are calculated. Finally, the method by which these Sub-Systems are integrated together to make the proposed speech-controlled 3D robot work is given.","PeriodicalId":374239,"journal":{"name":"2018 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131187869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
FPGA implementation of an adaptive LSB replacement based digital watermarking scheme FPGA实现一种基于LSB自适应替换的数字水印方案
2018 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2018-03-01 DOI: 10.1109/ISDCS.2018.8379652
S. Roy, A. Basu, Manisha Das, A. Chattopadhyay
{"title":"FPGA implementation of an adaptive LSB replacement based digital watermarking scheme","authors":"S. Roy, A. Basu, Manisha Das, A. Chattopadhyay","doi":"10.1109/ISDCS.2018.8379652","DOIUrl":"https://doi.org/10.1109/ISDCS.2018.8379652","url":null,"abstract":"Modern age communication prefers digital domain most for data processing and transmission as data augmentation and editing can be performed easily in digital domain. As a result, the purpose of copyright protection for data authentication has become a vital issue. Digital watermarking is an acceptable process with intention to shield copyright. Here a spatial domain watermarking scheme is set up based on adaptive LSB replacement. The hardware execution of the proposed watermark embedding and extracting system is also described using Field Programmable Gate Array (FPGA). The performance of this methodology, evaluated in terms of imperceptibility, robustness and payload capacity, implies the integrity of this watermarking logic. The reliability of this proposed scheme is also confirmed through comparing the proficiency of this process with some existing frameworks.","PeriodicalId":374239,"journal":{"name":"2018 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"165 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115465176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A low power intelligent helmet system 低功耗智能头盔系统
2018 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2018-03-01 DOI: 10.1109/ISDCS.2018.8379658
Albert Daimary, Meghna Goswami, R. K. Baruah
{"title":"A low power intelligent helmet system","authors":"Albert Daimary, Meghna Goswami, R. K. Baruah","doi":"10.1109/ISDCS.2018.8379658","DOIUrl":"https://doi.org/10.1109/ISDCS.2018.8379658","url":null,"abstract":"A low power intelligent helmet system is reported in this paper which ensures the safety of a two-wheeler rider. The primary concept behind the working of the system is that the ignition of a two-wheeler will be enabled only if the rider is wearing a helmet and not consuming alcohol. An alcohol sensor and helmet wearing sensitive switches are installed inside a helmet, which is connected wirelessly to the motorbike. The helmet is powered by a lithium ion battery which in turn is charged manually or by a solar panel, integrated outside the helmet. A fully functioning prototype of the reported switch based helmet system has been fabricated and all the necessary circuits are embedded inside the helmet and the motor bike. The proposed system has the unique characteristic of transmitting the appropriate condition of the signals for a predefined duration, followed by holding of these signals for the rest of the time at the receiving end for the proper functioning of the motorbike. Also, the alcohol detection circuit is automatically shut “OFF” after a predefined time. These features of the system results in around 15 times lesser power consumption.","PeriodicalId":374239,"journal":{"name":"2018 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128071830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Design of DRAM sense amplifier using 45nm technology 采用45nm技术的DRAM感测放大器的设计
2018 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2018-03-01 DOI: 10.1109/ISDCS.2018.8379656
Ankush Kumar, A. Pandey, P. Sahu, L. Chandra, R. Dwivedi, V. Mishra
{"title":"Design of DRAM sense amplifier using 45nm technology","authors":"Ankush Kumar, A. Pandey, P. Sahu, L. Chandra, R. Dwivedi, V. Mishra","doi":"10.1109/ISDCS.2018.8379656","DOIUrl":"https://doi.org/10.1109/ISDCS.2018.8379656","url":null,"abstract":"In very large scale integration (VLSI) circuits, power consumption plays a crucial role to design memory elements and digital systems. This work proposed the power savings in DRAM sense amplifier can be done by using FSPA-VLSA (Foot Switch PMOS Access Voltage Latch Type Sense Amplifier). Applying this technique in open bit architecture of DRAM Cell during read operation, a reduction in overall power consumption has been obtained approximately 81%. The proposed circuit also has advantages in low power VLSI/ULSI design. The circuit has been designed and implemented in Cadence virtuoso tools at 45nm Technology.","PeriodicalId":374239,"journal":{"name":"2018 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131074554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Adsorption probability of CH4, H2O and H2 in two-dimensional zinc oxide matrix: A prediction by DFT analysis 二维氧化锌基体对CH4、H2O和H2的吸附概率:DFT分析预测
2018 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2018-03-01 DOI: 10.1109/ISDCS.2018.8379673
N. S. Mahapatra, H. Rahaman, P. Bhattacharyya, K. Ghosh
{"title":"Adsorption probability of CH4, H2O and H2 in two-dimensional zinc oxide matrix: A prediction by DFT analysis","authors":"N. S. Mahapatra, H. Rahaman, P. Bhattacharyya, K. Ghosh","doi":"10.1109/ISDCS.2018.8379673","DOIUrl":"https://doi.org/10.1109/ISDCS.2018.8379673","url":null,"abstract":"The aim of the paper is to investigate the physisorption probability of CH4, H2O and H2 in graphene like two-dimensional (2D) Zinc oxide monolayer (g-ZnO) using density functional theory (DFT) incorporated with Quantumwise Atomistix Toolkit (ATK) (v.2016.4). For all the species, the adsorption distance, adsorption energy and charge transfer were calculated for three different adsorption sites on g-ZnO viz., atop Zn atom, atop oxygen atom and atop hollow position. It was found that H2O and CH4 show considerable adsorption probability in g-ZnO whereas H2 shows weak physisorption. Considerably high adsorption energy and charge transfer of H2O indicate that g-ZnO is suitable for designing humidity sensor.","PeriodicalId":374239,"journal":{"name":"2018 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"293 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131980514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Clifford+T-based quantum high speed multiplier 基于Clifford+的量子高速倍增器
2018 International Symposium on Devices, Circuits and Systems (ISDCS) Pub Date : 2018-03-01 DOI: 10.1109/ISDCS.2018.8379682
L. Biswal, Rakesh Das, A. Bhattacharjee, Sudip Ghosh, H. Rahaman
{"title":"Clifford+T-based quantum high speed multiplier","authors":"L. Biswal, Rakesh Das, A. Bhattacharjee, Sudip Ghosh, H. Rahaman","doi":"10.1109/ISDCS.2018.8379682","DOIUrl":"https://doi.org/10.1109/ISDCS.2018.8379682","url":null,"abstract":"Nowadays, rapid advancement in quantum algorithm towards achieving so-called quantum supremacy, calls for the design of high scalable quantum circuit. Quantum computers are very sensitive towards noise. To suppress inherent noise, the fault tolerant quantum circuit becomes desirable feature which can be achieved by using quantum error correction code. Surface code is one of the promising error correction code that addresses this issue. The Clifford+T group is one universal gates set which is used with surface code. In VLSI, multiplier circuit has very crucial role in the design of digital computer and becomes a pivotal in the application of DSP. Here, we have implemented a high speed quantum multiplier circuit using Clifford+T. At the end of this work, we evaluated some cost parameters like T-depth associated with the performance of quantum circuit as shown in the result section.","PeriodicalId":374239,"journal":{"name":"2018 International Symposium on Devices, Circuits and Systems (ISDCS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128608046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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