{"title":"Short Course: PLLs, Clocking, and Clock Distribution","authors":"B. Razavi","doi":"10.1109/ISSCC42613.2021.9365924","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365924","url":null,"abstract":"Provides an abstract of the tutorial presentation and may include a brief professional biography of the presenter. The complete presentation was not made available for publication as part of the conference proceedings.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116562414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Highly Digital 2210μm2 Resistor-Based Temperature Sensor with a 1-Point Trimmed Inaccuracy of ± 1.3 ° C (3 σ) from -55 ° C to 125 ° C in 65nm CMOS","authors":"J. Angevare, Youngcheol Chae, K. Makinwa","doi":"10.1109/ISSCC42613.2021.9365995","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365995","url":null,"abstract":"Microprocessors and SoCs employ multiple temperature sensors to prevent overheating and ensure reliable operation. Such sensors should be small (<10,000μm2) to monitor local hot-spots in dense layouts. They should also be moderately accurate (~1°C) up to high temperatures (≥125°C), so that the system throttling temperature can be set as close as possible to the maximum allowable die temperature. Furthermore, they should be fast (~1kS/s) and consume low power (tens of μW).","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115029040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"6.3 A 0.9V Dual-Channel Filtering-by-Aliasing Receiver Front-End Achieving +35dBm IIP3 and <-81dBm LO Leakage Supporting Intra-and Inter-Band Carrier Aggregation","authors":"Shi Bu, S. Pamarti","doi":"10.1109/ISSCC42613.2021.9366017","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9366017","url":null,"abstract":"Programmable receivers have drawn a lot of attention in recent years, especially those exploiting periodically time-varying (PTV) circuits. N-path filters and mixer-first receivers [1– 3] achieve sharp filtering and good linearity but can suffer from high LO leakage (> -70 dBm), which is not compliant with the FCC requirements [4]. In addition, they do not support multi-carrier operation very well [5].","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129997977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"[ISSCC 2021 Front cover]","authors":"","doi":"10.1109/isscc42613.2021.9365779","DOIUrl":"https://doi.org/10.1109/isscc42613.2021.9365779","url":null,"abstract":"","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132650888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tzu-Yuan Huang, M. N. Sasikanth, Sensen Li, Doohwan Jung, Min-Yu Huang, Hua Wang
{"title":"A 26-to-60GHz Continuous Coupler-Doherty Linear Power Amplifier for Over-An-Octave Back-Off Efficiency Enhancement","authors":"Tzu-Yuan Huang, M. N. Sasikanth, Sensen Li, Doohwan Jung, Min-Yu Huang, Hua Wang","doi":"10.1109/ISSCC42613.2021.9365858","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365858","url":null,"abstract":"It is envisioned that mm-wave wireless technologies will be the key enablers for 5G and beyond-5G wireless revolutions. To maximize the channel capacity, throughput, and frequency diversity, mm-wave wireless standards often mandate channels with GHz bandwidth (BW) over multiple non-contiguous bands. Also, as spectrally efficient highpeak-to-average power-ratio (PAPR) modulations such as OFDMs are widely employed, system dynamic range and linearity have become critical. Moreover, to compensate for the mm-wave path loss and enable diverse MIMO operations, there is an increasing need for complex high-density arrays with high system energy efficiency. These requirements have posed tremendous technical challenges on mm-wave front-ends, in particular PAs.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129449240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Higuchi, T. Kodama, Koji Kato, R. Fukuda, N. Tokiwa, Mitsuhiro Abe, Teruo Takagiwa, Y. Shimizu, Junji Musha, Katsuaki Sakurai, Jumpei Sato, T. Utsumi, Kazuhide Yoneya, Yasuhiro Suematsu, Toshifumi Hashimoto, T. Hioka, K. Yanagidaira, M. Kojima, J. Matsuno, Kei Shiraishi, Kensuke Yamamoto, Shintaro Hayashi, Tomoharu Hashiguchi, K. Inuzuka, Akio Sugahara, M. Honma, K. Tsunoda, Kazumasa Yamamoto, Takahiro Sugimoto, Tomofumi Fujimura, M. Kaneko, Hiroki Date, O. Kobayashi, Takatoshi Minamoto, R. Tachibana, I. Yamaguchi, Juan Lee, Venky Ramachandra, Srinivas Rajendra, Tianyu Tang, S. Darne, Jiwang Lee, Jason Li, Toru Miwa, Ryuji Yamashita, H. Sugawara, Naoki Ookuma, Masahiro Kano, Hiroyuki Mizukoshi, Y. Kuniyoshi, Mitsuyuki Watanabe, Kei Akiyama, H. Mori, Akira Arimizu, Yoshito Katano, M. Ehama, H. Maejima, K. Hosono, Masahiro Yoshihara
{"title":"30.4 A 1Tb 3b/Cell 3D-Flash Memory in a 170+ Word-Line-Layer Technology","authors":"T. Higuchi, T. Kodama, Koji Kato, R. Fukuda, N. Tokiwa, Mitsuhiro Abe, Teruo Takagiwa, Y. Shimizu, Junji Musha, Katsuaki Sakurai, Jumpei Sato, T. Utsumi, Kazuhide Yoneya, Yasuhiro Suematsu, Toshifumi Hashimoto, T. Hioka, K. Yanagidaira, M. Kojima, J. Matsuno, Kei Shiraishi, Kensuke Yamamoto, Shintaro Hayashi, Tomoharu Hashiguchi, K. Inuzuka, Akio Sugahara, M. Honma, K. Tsunoda, Kazumasa Yamamoto, Takahiro Sugimoto, Tomofumi Fujimura, M. Kaneko, Hiroki Date, O. Kobayashi, Takatoshi Minamoto, R. Tachibana, I. Yamaguchi, Juan Lee, Venky Ramachandra, Srinivas Rajendra, Tianyu Tang, S. Darne, Jiwang Lee, Jason Li, Toru Miwa, Ryuji Yamashita, H. Sugawara, Naoki Ookuma, Masahiro Kano, Hiroyuki Mizukoshi, Y. Kuniyoshi, Mitsuyuki Watanabe, Kei Akiyama, H. Mori, Akira Arimizu, Yoshito Katano, M. Ehama, H. Maejima, K. Hosono, Masahiro Yoshihara","doi":"10.1109/ISSCC42613.2021.9366003","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9366003","url":null,"abstract":"This work demonstrates a novel 1Tb 3D Flash memory chip that has an area efficiency of 10.4Gb/mm2 in a 3b/cell technology. Using a circuit under array (CUA) design technique and over 170 word-line (WL) layers, the chip achieves 33% higher bit density than prior 3b/cell work [1], and better density than in 4b/cell technology [3]. This paper discusses the challenges advanced 3D Flash memories face: using over 100 WL layers results in large parasitic loads and decreases read/program speed, and its complicated operation increases test costs. On the other hand, as high bandwidth is also required, this chip supports a 2.0Gbps IO transfer rate, while maintaining signal integrity. This work introduces four new key technologies to address these difficulties. 1) Asynchronous independent plane read (AIPR), with a 4-plane architecture to improve system-level performance. 2) Enhanced sensing that enables faster read time $(t_{R})$. 3) IO-DCC (duty cycle correction) training for high-speed DDR operation. 4) A scan chain to improve test coverage and cost effectiveness.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129816138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Fully Integrated 2.7µW -70.2dBm-Sensitivity Wake-Up Receiver with Charge-Domain Analog Front-End, -16.5dB-SIR, FEC and Cryptographic Checksum","authors":"","doi":"10.1109/ISSCC42613.2021.9365806","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365806","url":null,"abstract":"Ultra-low-power (ULP) receivers are gaining traction in consumer and industrial IoT solutions as standards such as WiFi 802.11ba, BLE, and NB-IoT have adopted wakeup messages into their protocols to reduce synchronization energy overhead. ULP wakeup receivers (WRX) enable lower average power, lower latency, and precise time synchronization which leads to more dense network deployments [1–5]. This paper presents a $2.7 mu$W WRX that supports a simplified 802.15.4g MAC/PHY baseband, RSSI and clear channel assessment (CCA), forward error correction (FEC), and cryptographic checksum. The novelty of this WRX is the parallel-path rectifier and charge-domain analog front-end (AFE), which provides low power, wide dynamic range, pulsed interference rejection, and reliable operation across harsh environments and industrial wireless conditions in real-world deployments.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132483429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Beikmirza, Yiyu Shen, M. Mehrpoo, M. Hashemi, Dieuwert P. N. Mul, L. D. Vreede, M. Alavi
{"title":"6.2 A 4-Way Doherty Digital Transmitter Featuring 50%-LO Signed IQ Interleave Upconversion with more than 27dBm Peak Power and 40% Drain Efficiency at 10dB Power Back-Off Operating in the 5GHz Band","authors":"M. Beikmirza, Yiyu Shen, M. Mehrpoo, M. Hashemi, Dieuwert P. N. Mul, L. D. Vreede, M. Alavi","doi":"10.1109/ISSCC42613.2021.9365831","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365831","url":null,"abstract":"Recently, digital transmitters (DTXs) that feature arrays of controlled digital PA (DPA) cells have become increasingly popular since they directly benefit from nanoscale CMOS technology, yielding reduced die area and highly efficient operation [1] –[6]. For wideband applications, I/Q DTXs are considered superior over their polar counterparts due to their linear I/Q operation, which avoids bandwidth expansion. Nevertheless, I/Q DTXs can suffer from the interaction between their I and Q paths, especially at higher power levels, giving rise to an I/Q image and nonlinearity. To tackle this issue, an IQ interleaved upconverter has been introduced [1]. However, its 25%-LO requirement restricts the operational frequency to below 5GHz. The diamond-shaped mapping technique, presented in [2], uses 50% LOs and a different I and Q combining method but suffers from nonlinearity due to a clipping operation. Besides, the large peak-to-average power ratio (PAPR) in modern wireless standards requires the DTX to operate in deep power back-off (DPBO), degrading its average efficiency. To target applications requiring large modulation bandwidth, high spectral purity and average efficiency, we present a DTX with a signed IQ interleaved upconversion approach based on 50%-LO clock distribution, which enables close to perfect orthogonal I/Q summation. To enhance its average efficiency, a compact, 4-way Doherty DPA architecture is introduced.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116279654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Ogi, T. Takatsuka, Kazuki Hizu, Yutaka Inaoka, Hongbo Zhu, Yasuhisa Tochigi, Y. Tashiro, F. Sano, Yusuke Murakawa, Makoto Nakamura, Y. Oike
{"title":"7.5 A 250fps 124dB Dynamic-Range SPAD Image Sensor Stacked with Pixel-Parallel Photon Counter Employing Sub-Frame Extrapolating Architecture for Motion Artifact Suppression","authors":"J. Ogi, T. Takatsuka, Kazuki Hizu, Yutaka Inaoka, Hongbo Zhu, Yasuhisa Tochigi, Y. Tashiro, F. Sano, Yusuke Murakawa, Makoto Nakamura, Y. Oike","doi":"10.1109/ISSCC42613.2021.9365977","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365977","url":null,"abstract":"Photon-count imaging has been proposed as a promising technology to realize image capture with noiseless readout and high dynamic range (HDR) [1]–[7]. In addition, for industrial and scientific applications, a global shutter exposure with motion artifact suppression is essential. A single-photon avalanche diode (SPAD) image sensor is well matched to the photon-counting architecture by shrinking the SPAD pixel size and stacking a logic chip with pixel-parallel Cu–Cu connections. A pixel-parallel photon counter, however, requires many counter bits in a pixel for HDR operation. This makes it difficult to shrink the pixel size and lower the power consumption, owing to the substantial number of SPAD activations under high light conditions [2]. Inter-frame mode switching between digital photon count and analog accumulation avoids the power increase under high light conditions, but it suffers from a dip in the signal-to-noise ratio (SNR) and/or motion artifact in reproducing an HDR image [3], [4]. An approach reducing SPAD activations under high light conditions can reduce the power consumption [5]–[7], but the combination of long- and short-exposure frames for HDR [5], [6] still suffers from the dip in SNR like conventional multi-exposure image sensors [8], even if these techniques can suppress motion artifacts owing to sub-frame readout.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116292953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Adaptive Intelligence in The New Computing Era","authors":"V. Peng","doi":"10.1109/ISSCC42613.2021.9365851","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365851","url":null,"abstract":"Connectivity is becoming ubiquitous with everything being connected all the time. Everything from streetlights to smart city cameras, automobiles, and appliances will be connected and generating continuous data. The unprecedented increase in the number of devices that generate data, most of which is unstructured, and the increase in the volume of data has led to a change in the way data is analysed, transported, and stored. This connectivity requires high aggregated bandwidth, low-latency as well as security. This has accelerated industry standards across many areas, including wireless, wireline, automotive, and data centers. This new era requires distributed computing that is also intelligent. More data needs to be processed where it is generated, while it is being transported and while it is at rest. At the same time, improvement in silicon technology has slowed down. Traditional computing platforms and architectures are unable to sufficiently scale to address the changing needs.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131802721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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