30.4 A 1Tb 3b/Cell 3D-Flash Memory in a 170+ Word-Line-Layer Technology

2021 IEEE International Solid- State Circuits Conference (ISSCC) Pub Date : 2021-02-13 DOI:10.1109/ISSCC42613.2021.9366003

T. Higuchi, T. Kodama, Koji Kato, R. Fukuda, N. Tokiwa, Mitsuhiro Abe, Teruo Takagiwa, Y. Shimizu, Junji Musha, Katsuaki Sakurai, Jumpei Sato, T. Utsumi, Kazuhide Yoneya, Yasuhiro Suematsu, Toshifumi Hashimoto, T. Hioka, K. Yanagidaira, M. Kojima, J. Matsuno, Kei Shiraishi, Kensuke Yamamoto, Shintaro Hayashi, Tomoharu Hashiguchi, K. Inuzuka, Akio Sugahara, M. Honma, K. Tsunoda, Kazumasa Yamamoto, Takahiro Sugimoto, Tomofumi Fujimura, M. Kaneko, Hiroki Date, O. Kobayashi, Takatoshi Minamoto, R. Tachibana, I. Yamaguchi, Juan Lee, Venky Ramachandra, Srinivas Rajendra, Tianyu Tang, S. Darne, Jiwang Lee, Jason Li, Toru Miwa, Ryuji Yamashita, H. Sugawara, Naoki Ookuma, Masahiro Kano, Hiroyuki Mizukoshi, Y. Kuniyoshi, Mitsuyuki Watanabe, Kei Akiyama, H. Mori, Akira Arimizu, Yoshito Katano, M. Ehama, H. Maejima, K. Hosono, Masahiro Yoshihara

{"title":"30.4 A 1Tb 3b/Cell 3D-Flash Memory in a 170+ Word-Line-Layer Technology","authors":"T. Higuchi, T. Kodama, Koji Kato, R. Fukuda, N. Tokiwa, Mitsuhiro Abe, Teruo Takagiwa, Y. Shimizu, Junji Musha, Katsuaki Sakurai, Jumpei Sato, T. Utsumi, Kazuhide Yoneya, Yasuhiro Suematsu, Toshifumi Hashimoto, T. Hioka, K. Yanagidaira, M. Kojima, J. Matsuno, Kei Shiraishi, Kensuke Yamamoto, Shintaro Hayashi, Tomoharu Hashiguchi, K. Inuzuka, Akio Sugahara, M. Honma, K. Tsunoda, Kazumasa Yamamoto, Takahiro Sugimoto, Tomofumi Fujimura, M. Kaneko, Hiroki Date, O. Kobayashi, Takatoshi Minamoto, R. Tachibana, I. Yamaguchi, Juan Lee, Venky Ramachandra, Srinivas Rajendra, Tianyu Tang, S. Darne, Jiwang Lee, Jason Li, Toru Miwa, Ryuji Yamashita, H. Sugawara, Naoki Ookuma, Masahiro Kano, Hiroyuki Mizukoshi, Y. Kuniyoshi, Mitsuyuki Watanabe, Kei Akiyama, H. Mori, Akira Arimizu, Yoshito Katano, M. Ehama, H. Maejima, K. Hosono, Masahiro Yoshihara","doi":"10.1109/ISSCC42613.2021.9366003","DOIUrl":null,"url":null,"abstract":"This work demonstrates a novel 1Tb 3D Flash memory chip that has an area efficiency of 10.4Gb/mm2 in a 3b/cell technology. Using a circuit under array (CUA) design technique and over 170 word-line (WL) layers, the chip achieves 33% higher bit density than prior 3b/cell work [1], and better density than in 4b/cell technology [3]. This paper discusses the challenges advanced 3D Flash memories face: using over 100 WL layers results in large parasitic loads and decreases read/program speed, and its complicated operation increases test costs. On the other hand, as high bandwidth is also required, this chip supports a 2.0Gbps IO transfer rate, while maintaining signal integrity. This work introduces four new key technologies to address these difficulties. 1) Asynchronous independent plane read (AIPR), with a 4-plane architecture to improve system-level performance. 2) Enhanced sensing that enables faster read time $(t_{R})$. 3) IO-DCC (duty cycle correction) training for high-speed DDR operation. 4) A scan chain to improve test coverage and cost effectiveness.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC42613.2021.9366003","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 10

Abstract

This work demonstrates a novel 1Tb 3D Flash memory chip that has an area efficiency of 10.4Gb/mm2 in a 3b/cell technology. Using a circuit under array (CUA) design technique and over 170 word-line (WL) layers, the chip achieves 33% higher bit density than prior 3b/cell work [1], and better density than in 4b/cell technology [3]. This paper discusses the challenges advanced 3D Flash memories face: using over 100 WL layers results in large parasitic loads and decreases read/program speed, and its complicated operation increases test costs. On the other hand, as high bandwidth is also required, this chip supports a 2.0Gbps IO transfer rate, while maintaining signal integrity. This work introduces four new key technologies to address these difficulties. 1) Asynchronous independent plane read (AIPR), with a 4-plane architecture to improve system-level performance. 2) Enhanced sensing that enables faster read time $(t_{R})$. 3) IO-DCC (duty cycle correction) training for high-speed DDR operation. 4) A scan chain to improve test coverage and cost effectiveness.

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采用170+字线层技术的30.4 A 1Tb 3b/Cell 3d闪存

这项工作展示了一种新型的1Tb 3D闪存芯片，在3b/cell技术中具有10.4Gb/mm2的面积效率。采用阵列下电路(CUA)设计技术和超过170个字行(WL)层，该芯片的比特密度比之前的3b/cell工作高33%[1]，比4b/cell技术的密度更高[3]。本文讨论了先进的3D闪存面临的挑战:使用超过100个WL层会导致较大的寄生负载和降低读取/程序速度，其复杂的操作增加了测试成本。另一方面，由于还需要高带宽，因此该芯片在保持信号完整性的同时支持2.0Gbps的IO传输速率。本文介绍了四种新的关键技术来解决这些困难。1)异步独立平面读取(AIPR)，采用4平面架构，提高系统级性能。2)增强传感，使读取时间更快$(t_{R})$。3)高速DDR操作IO-DCC(占空比校正)训练。4)扫描链，以提高测试覆盖率和成本效益。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2021 IEEE International Solid- State Circuits Conference (ISSCC)

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