T. Higuchi, T. Kodama, Koji Kato, R. Fukuda, N. Tokiwa, Mitsuhiro Abe, Teruo Takagiwa, Y. Shimizu, Junji Musha, Katsuaki Sakurai, Jumpei Sato, T. Utsumi, Kazuhide Yoneya, Yasuhiro Suematsu, Toshifumi Hashimoto, T. Hioka, K. Yanagidaira, M. Kojima, J. Matsuno, Kei Shiraishi, Kensuke Yamamoto, Shintaro Hayashi, Tomoharu Hashiguchi, K. Inuzuka, Akio Sugahara, M. Honma, K. Tsunoda, Kazumasa Yamamoto, Takahiro Sugimoto, Tomofumi Fujimura, M. Kaneko, Hiroki Date, O. Kobayashi, Takatoshi Minamoto, R. Tachibana, I. Yamaguchi, Juan Lee, Venky Ramachandra, Srinivas Rajendra, Tianyu Tang, S. Darne, Jiwang Lee, Jason Li, Toru Miwa, Ryuji Yamashita, H. Sugawara, Naoki Ookuma, Masahiro Kano, Hiroyuki Mizukoshi, Y. Kuniyoshi, Mitsuyuki Watanabe, Kei Akiyama, H. Mori, Akira Arimizu, Yoshito Katano, M. Ehama, H. Maejima, K. Hosono, Masahiro Yoshihara
{"title":"采用170+字线层技术的30.4 A 1Tb 3b/Cell 3d闪存","authors":"T. Higuchi, T. Kodama, Koji Kato, R. Fukuda, N. Tokiwa, Mitsuhiro Abe, Teruo Takagiwa, Y. Shimizu, Junji Musha, Katsuaki Sakurai, Jumpei Sato, T. Utsumi, Kazuhide Yoneya, Yasuhiro Suematsu, Toshifumi Hashimoto, T. Hioka, K. Yanagidaira, M. Kojima, J. Matsuno, Kei Shiraishi, Kensuke Yamamoto, Shintaro Hayashi, Tomoharu Hashiguchi, K. Inuzuka, Akio Sugahara, M. Honma, K. Tsunoda, Kazumasa Yamamoto, Takahiro Sugimoto, Tomofumi Fujimura, M. Kaneko, Hiroki Date, O. Kobayashi, Takatoshi Minamoto, R. Tachibana, I. Yamaguchi, Juan Lee, Venky Ramachandra, Srinivas Rajendra, Tianyu Tang, S. Darne, Jiwang Lee, Jason Li, Toru Miwa, Ryuji Yamashita, H. Sugawara, Naoki Ookuma, Masahiro Kano, Hiroyuki Mizukoshi, Y. Kuniyoshi, Mitsuyuki Watanabe, Kei Akiyama, H. Mori, Akira Arimizu, Yoshito Katano, M. Ehama, H. Maejima, K. Hosono, Masahiro Yoshihara","doi":"10.1109/ISSCC42613.2021.9366003","DOIUrl":null,"url":null,"abstract":"This work demonstrates a novel 1Tb 3D Flash memory chip that has an area efficiency of 10.4Gb/mm2 in a 3b/cell technology. Using a circuit under array (CUA) design technique and over 170 word-line (WL) layers, the chip achieves 33% higher bit density than prior 3b/cell work [1], and better density than in 4b/cell technology [3]. This paper discusses the challenges advanced 3D Flash memories face: using over 100 WL layers results in large parasitic loads and decreases read/program speed, and its complicated operation increases test costs. On the other hand, as high bandwidth is also required, this chip supports a 2.0Gbps IO transfer rate, while maintaining signal integrity. This work introduces four new key technologies to address these difficulties. 1) Asynchronous independent plane read (AIPR), with a 4-plane architecture to improve system-level performance. 2) Enhanced sensing that enables faster read time $(t_{R})$. 3) IO-DCC (duty cycle correction) training for high-speed DDR operation. 4) A scan chain to improve test coverage and cost effectiveness.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"30.4 A 1Tb 3b/Cell 3D-Flash Memory in a 170+ Word-Line-Layer Technology\",\"authors\":\"T. Higuchi, T. Kodama, Koji Kato, R. Fukuda, N. Tokiwa, Mitsuhiro Abe, Teruo Takagiwa, Y. Shimizu, Junji Musha, Katsuaki Sakurai, Jumpei Sato, T. Utsumi, Kazuhide Yoneya, Yasuhiro Suematsu, Toshifumi Hashimoto, T. Hioka, K. Yanagidaira, M. Kojima, J. Matsuno, Kei Shiraishi, Kensuke Yamamoto, Shintaro Hayashi, Tomoharu Hashiguchi, K. Inuzuka, Akio Sugahara, M. Honma, K. Tsunoda, Kazumasa Yamamoto, Takahiro Sugimoto, Tomofumi Fujimura, M. Kaneko, Hiroki Date, O. Kobayashi, Takatoshi Minamoto, R. Tachibana, I. Yamaguchi, Juan Lee, Venky Ramachandra, Srinivas Rajendra, Tianyu Tang, S. Darne, Jiwang Lee, Jason Li, Toru Miwa, Ryuji Yamashita, H. Sugawara, Naoki Ookuma, Masahiro Kano, Hiroyuki Mizukoshi, Y. Kuniyoshi, Mitsuyuki Watanabe, Kei Akiyama, H. Mori, Akira Arimizu, Yoshito Katano, M. Ehama, H. Maejima, K. Hosono, Masahiro Yoshihara\",\"doi\":\"10.1109/ISSCC42613.2021.9366003\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work demonstrates a novel 1Tb 3D Flash memory chip that has an area efficiency of 10.4Gb/mm2 in a 3b/cell technology. Using a circuit under array (CUA) design technique and over 170 word-line (WL) layers, the chip achieves 33% higher bit density than prior 3b/cell work [1], and better density than in 4b/cell technology [3]. This paper discusses the challenges advanced 3D Flash memories face: using over 100 WL layers results in large parasitic loads and decreases read/program speed, and its complicated operation increases test costs. On the other hand, as high bandwidth is also required, this chip supports a 2.0Gbps IO transfer rate, while maintaining signal integrity. This work introduces four new key technologies to address these difficulties. 1) Asynchronous independent plane read (AIPR), with a 4-plane architecture to improve system-level performance. 2) Enhanced sensing that enables faster read time $(t_{R})$. 3) IO-DCC (duty cycle correction) training for high-speed DDR operation. 4) A scan chain to improve test coverage and cost effectiveness.\",\"PeriodicalId\":371093,\"journal\":{\"name\":\"2021 IEEE International Solid- State Circuits Conference (ISSCC)\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-02-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE International Solid- State Circuits Conference (ISSCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC42613.2021.9366003\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC42613.2021.9366003","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
30.4 A 1Tb 3b/Cell 3D-Flash Memory in a 170+ Word-Line-Layer Technology
This work demonstrates a novel 1Tb 3D Flash memory chip that has an area efficiency of 10.4Gb/mm2 in a 3b/cell technology. Using a circuit under array (CUA) design technique and over 170 word-line (WL) layers, the chip achieves 33% higher bit density than prior 3b/cell work [1], and better density than in 4b/cell technology [3]. This paper discusses the challenges advanced 3D Flash memories face: using over 100 WL layers results in large parasitic loads and decreases read/program speed, and its complicated operation increases test costs. On the other hand, as high bandwidth is also required, this chip supports a 2.0Gbps IO transfer rate, while maintaining signal integrity. This work introduces four new key technologies to address these difficulties. 1) Asynchronous independent plane read (AIPR), with a 4-plane architecture to improve system-level performance. 2) Enhanced sensing that enables faster read time $(t_{R})$. 3) IO-DCC (duty cycle correction) training for high-speed DDR operation. 4) A scan chain to improve test coverage and cost effectiveness.
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