2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)最新文献

筛选
英文 中文
A fast and precise eye-diagram estimation method for a channel of a pair of differential microstrip lines on PCB with arbitrary terminations 一种快速精确的任意端部PCB差分微带线通道眼图估计方法
2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS) Pub Date : 2009-12-01 DOI: 10.1109/EDAPS.2009.5403987
Jeonghyeon Cho, Eakhwan Song, J. Shim, Yujeong Shim, Joungho Kim
{"title":"A fast and precise eye-diagram estimation method for a channel of a pair of differential microstrip lines on PCB with arbitrary terminations","authors":"Jeonghyeon Cho, Eakhwan Song, J. Shim, Yujeong Shim, Joungho Kim","doi":"10.1109/EDAPS.2009.5403987","DOIUrl":"https://doi.org/10.1109/EDAPS.2009.5403987","url":null,"abstract":"In this paper, we propose a fast and precise eye-diagram estimation method for a channel of a pair of differential microstrip lines on PCBs with arbitrary source and load terminations. The voltage transfer function of a channel is investigated as a quick measure of the signal integrity of a channel and the DDJ and eye-opening voltage values are precisely estimated by using a modified peak distortion analysis. The efficiency and the accuracy of the proposed eye-diagram estimation method were successfully verified through HSPICE simulations.","PeriodicalId":370741,"journal":{"name":"2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130309667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A package pin-block planner considering chip-package interconnects optimization 考虑芯片封装互连优化的封装引脚块规划
2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS) Pub Date : 2009-12-01 DOI: 10.1109/EDAPS.2009.5404013
R. Lee, Hung-Ming Chen
{"title":"A package pin-block planner considering chip-package interconnects optimization","authors":"R. Lee, Hung-Ming Chen","doi":"10.1109/EDAPS.2009.5404013","DOIUrl":"https://doi.org/10.1109/EDAPS.2009.5404013","url":null,"abstract":"In this paper, we propose an improved pin-block placer to optimize the objectives of shorter path length and equi-length on package routing. This placer keeps the same minimized package size as the recent work and ensure that signal integrity (SI), power delivery integrity (PI) and routability (RA) can still be considered with significant reduction in design cost. It is achieved by relaxing the restriction of pin-block side and order on the package, usually specified by package designers. The experimental results on industrial chipset design cases show that the average improvement of our pin-block planner is over 40% when comparing the design cost with the previous work, among which we have one case over a thousand pins.","PeriodicalId":370741,"journal":{"name":"2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128538573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A thin film thermoelectric cooler for chip-on-board direct assembly 一种用于片上直接组装的薄膜热电冷却器
2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS) Pub Date : 2009-12-01 DOI: 10.1109/EDAPS.2009.5403990
Hyunju Lee, Soonseo Park, Sung-Kyo Cho, Hyojong Kim, Shiho Kim
{"title":"A thin film thermoelectric cooler for chip-on-board direct assembly","authors":"Hyunju Lee, Soonseo Park, Sung-Kyo Cho, Hyojong Kim, Shiho Kim","doi":"10.1109/EDAPS.2009.5403990","DOIUrl":"https://doi.org/10.1109/EDAPS.2009.5403990","url":null,"abstract":"A thin film solid state cooler for COB direct assembly using supperlattice based thermoelectric material is reported. The embedded cooler attached between the die chip and metal plate can provide site-specific cooling as well as active on-demand cooling. This demonstration offers the possibility of thin film active cooling for the COB direct assembly. The high power density of chip-on-Board would be no longer be limited by cooling capability. This technology can be extended to the case of hot spot cooling for COB assembly that can be selectively switched on and off depending on which part of the chip is in critical need of cooling at any point of time.","PeriodicalId":370741,"journal":{"name":"2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127255218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Modeling and analysis of electromagnetic bandgap structures on power distribution network 配电网电磁带隙结构的建模与分析
2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS) Pub Date : 2009-12-01 DOI: 10.1109/EDAPS.2009.5403992
Sang-Gyu Kim, H. Kim, Hee-Do Kang, J. Yook
{"title":"Modeling and analysis of electromagnetic bandgap structures on power distribution network","authors":"Sang-Gyu Kim, H. Kim, Hee-Do Kang, J. Yook","doi":"10.1109/EDAPS.2009.5403992","DOIUrl":"https://doi.org/10.1109/EDAPS.2009.5403992","url":null,"abstract":"Transmission line method (TLM) is applied for analysis of a conventional electromagnetic bandgap (EBG) structure with arbitrary shaped power/ground plane. The fast and accurate modeling by TLM shows the computationally efficient results with respect to full-wave electromagnetic analysis. More-over it is shown that suppression bandwidth of a EBG structure can be easily analyzed by stepped impedance filter and the calculated bandwidth is identical to the measured.","PeriodicalId":370741,"journal":{"name":"2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130846824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Extended analysis of SSN effect on phase-locked loop (PLL) circuit SSN对锁相环(PLL)电路影响的扩展分析
2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS) Pub Date : 2009-12-01 DOI: 10.1109/EDAPS.2009.5404005
J. Kho, C. I. Loh, Wui Hung Moo, C. Fong, M. Wong
{"title":"Extended analysis of SSN effect on phase-locked loop (PLL) circuit","authors":"J. Kho, C. I. Loh, Wui Hung Moo, C. Fong, M. Wong","doi":"10.1109/EDAPS.2009.5404005","DOIUrl":"https://doi.org/10.1109/EDAPS.2009.5404005","url":null,"abstract":"Electronic devices are increasingly susceptible to simultaneous switching noise (SSN) as devices shrink in size and operate at lower voltage to achieve higher speed. This is a major concern in high-speed system designs as SSN causes voltage and timing variations which affect signal integrity. Consequently, it is imperative that electronic system designers pay strict attention to signal integrity whether it is on the chip level or on the system level. This paper analyzes the output buffer SSN effect on the phase-locked loop (PLL) input pins, PLL output pins, and PLL power supplies using an Altera FPGA device. Experimental results show that direct PLL jitter transfer principle cannot be applied in a straight forward manner because of the wide spectrum and asynchronous nature of SSN. However, the PLL circuit is still effective in filtering the noise that is attacking the PLL input signal. This paper also shows that SSN greatly affects the PLL power distribution network (PDN) especially when the noise coupled into the PDN have the same frequency as the PDN resonance. In addition, it is also shown that SSN do not directly attack the PLL circuit through its output. These findings assist Altera's customers and electronic system designers in optimizing PLL performance for error-free device designs. Furthermore, the findings provide a basis future PLL design improvements.","PeriodicalId":370741,"journal":{"name":"2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125095456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Filter integration in ultra thin organic substrate via 3D stitched capacitor 在超薄有机衬底上通过3D缝合电容器集成滤波器
2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS) Pub Date : 2009-12-01 DOI: 10.1109/EDAPS.2009.5404004
S. Min, Seunghyun Hwang, Daehyun Chung, M. Swaminathan, V. Sridharan, H. Chan, Fuhan Liu, V. Sundaram, R. Tummala
{"title":"Filter integration in ultra thin organic substrate via 3D stitched capacitor","authors":"S. Min, Seunghyun Hwang, Daehyun Chung, M. Swaminathan, V. Sridharan, H. Chan, Fuhan Liu, V. Sundaram, R. Tummala","doi":"10.1109/EDAPS.2009.5404004","DOIUrl":"https://doi.org/10.1109/EDAPS.2009.5404004","url":null,"abstract":"This paper presents filters integrated in ultra thin multilayer organic substrate using 3D stitched capacitor alleviating shunt parasitics and providing tunable capacitors. Insertion loss of less than 2.2dB, return loss of greater than 15dB at 2.4 GHz and attenuation of greater than 30dB below 2.0 GHz and at 4.7 GHz were measured. The measured results showed good agreement with simulated results. This paper demonstrated 2.4 GHz bandpass filters with size of 2.2mm × 3.0mm × 0.2mm (1.2mm3) in ultra thin organic RXP substrate.","PeriodicalId":370741,"journal":{"name":"2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133779893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Power distribution network co-simulation for cost-effective system design 配电网协同仿真技术在系统设计中的应用
2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS) Pub Date : 2009-12-01 DOI: 10.1109/EDAPS.2009.5403995
J. Hsu, Jack Lin, Tung-Yang Chen, Wei-Da Guo, Sam Yang, R. Lee
{"title":"Power distribution network co-simulation for cost-effective system design","authors":"J. Hsu, Jack Lin, Tung-Yang Chen, Wei-Da Guo, Sam Yang, R. Lee","doi":"10.1109/EDAPS.2009.5403995","DOIUrl":"https://doi.org/10.1109/EDAPS.2009.5403995","url":null,"abstract":"The power distribution network (PDN) analysis, including chip, quad-flat-package (QFP) and two-layer board, was presented for the cost-effective system design in the high-speed IO application. The physical interaction between the high-inductive shared off-chip design and capacitive on-chip network was discussed to figure out the related potential issues, such as anti-resonance and the serious interference in PDN. Finally, the integrated analysis with frequency-dependent PDN characteristics, instead of the traditional complicated spice model, was analyzed and validated in the time domain to correlate with the simultaneously switching noise in the frequency domain finding.","PeriodicalId":370741,"journal":{"name":"2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)","volume":"303 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121266995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
IRDrop analysis in power delivery network design 输电网设计中的IRDrop分析
2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS) Pub Date : 2009-12-01 DOI: 10.1109/EDAPS.2009.5403974
W. Dai
{"title":"IRDrop analysis in power delivery network design","authors":"W. Dai","doi":"10.1109/EDAPS.2009.5403974","DOIUrl":"https://doi.org/10.1109/EDAPS.2009.5403974","url":null,"abstract":"This paper introduces a process that allows customers to do IRDrop analysis on the package/SiP and PCB level. The component information such as the package model, power consumption and voltage regulator module (VRM) as well as power delivery network circuit can be used at the package and board level to perform static IRDrop analysis. The power consumption is used to obtain the current excitation while the VRM pins are used to provide the power supply. For the complicated package and PCB geometry structure, the progressive mesh scheme is used to extract the DC circuit model for their power delivery network. In order to meet the tolerance of current and voltage drop, the required VRM and IC components locations as well as stackup can be optimized according to the voltage drop in DC domain. The user can also view the voltage drop, current and temperature rise.","PeriodicalId":370741,"journal":{"name":"2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128717603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Investigation of the gyro-resonance region modes by using the MoM for plasma column loaded cylindrical waveguide 等离子体柱载圆柱波导陀螺共振区模的MoM研究
2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS) Pub Date : 2009-12-01 DOI: 10.1109/EDAPS.2009.5403978
E. Kelebekler
{"title":"Investigation of the gyro-resonance region modes by using the MoM for plasma column loaded cylindrical waveguide","authors":"E. Kelebekler","doi":"10.1109/EDAPS.2009.5403978","DOIUrl":"https://doi.org/10.1109/EDAPS.2009.5403978","url":null,"abstract":"In this study, the dispersion curves of the plasma modes, which exist in gyroresonance region, have been obtained by using Method of Moment (MoM) for the plasma column loaded cylindrical waveguide. In the study, the first three modes, which have lowest degree, have been investigated. The validation of the method has been tested by comparing the exact solution of the structure which exists in the literature. Comparative results have been presented numerically and graphically. Besides absolute error curves have been given for each structure.","PeriodicalId":370741,"journal":{"name":"2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131016163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A new FDTD algorithm based on alternating-direction explicit method 一种基于交替方向显式法的时域有限差分新算法
2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS) Pub Date : 2009-12-01 DOI: 10.1109/EDAPS.2009.5404012
M. Unno, S. Aono, H. Asai
{"title":"A new FDTD algorithm based on alternating-direction explicit method","authors":"M. Unno, S. Aono, H. Asai","doi":"10.1109/EDAPS.2009.5404012","DOIUrl":"https://doi.org/10.1109/EDAPS.2009.5404012","url":null,"abstract":"In this paper, a new finite-Difference Time-Domain (FDTD) method is proposed in order to eliminate the Courant-Friedrich-Levy (CFL) condition restraint. This new algorithm is based on an alternating-direction explicit method. This work is the first application of the Alternating-Direction Explicit (ADE) method to the FDTD method. In this report, numerical formulations and some simulation results are presented. Furthermore, the results by ADE-FDTD method are compared with the results by the conventional FDTD method. As a result, it is confirmed that the proposed method is almost unconditionally stable and superior to the conventional one.","PeriodicalId":370741,"journal":{"name":"2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132648954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信