Power distribution network co-simulation for cost-effective system design

Abstract

The power distribution network (PDN) analysis, including chip, quad-flat-package (QFP) and two-layer board, was presented for the cost-effective system design in the high-speed IO application. The physical interaction between the high-inductive shared off-chip design and capacitive on-chip network was discussed to figure out the related potential issues, such as anti-resonance and the serious interference in PDN. Finally, the integrated analysis with frequency-dependent PDN characteristics, instead of the traditional complicated spice model, was analyzed and validated in the time domain to correlate with the simultaneously switching noise in the frequency domain finding.