A package pin-block planner considering chip-package interconnects optimization

Abstract

In this paper, we propose an improved pin-block placer to optimize the objectives of shorter path length and equi-length on package routing. This placer keeps the same minimized package size as the recent work and ensure that signal integrity (SI), power delivery integrity (PI) and routability (RA) can still be considered with significant reduction in design cost. It is achieved by relaxing the restriction of pin-block side and order on the package, usually specified by package designers. The experimental results on industrial chipset design cases show that the average improvement of our pin-block planner is over 40% when comparing the design cost with the previous work, among which we have one case over a thousand pins.