Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design最新文献_第4页

DeePEB

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design Pub Date : 2022-10-30 DOI: 10.1145/3508352.3549398

Qipan Wang, Xiaohan Gao, Yibo Lin, Runsheng Wang, Ru Huang

引用次数: 0

Seprox Seprox

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design Pub Date : 2022-10-30 DOI: 10.1145/3508352.3549435

A. M. Parvathy, Sarada Krithivasan, Sanchari Sen, Anand Raghunathan

{"title":"Seprox","authors":"A. M. Parvathy, Sarada Krithivasan, Sanchari Sen, Anand Raghunathan","doi":"10.1145/3508352.3549435","DOIUrl":"https://doi.org/10.1145/3508352.3549435","url":null,"abstract":"Compression techniques such as quantization and pruning are indispensable for deploying state-of-the-art Deep Neural Networks (DNNs) on resource-constrained edge devices. Quantization is widely used in practice – many commercial platforms already support 8bits, with recent trends towards ultra-low precision (4-bits and below). Pruning, which increases network sparsity (incidence of zero-valued weights), enables compression by storing only the nonzero weights and their indices. Unfortunately, the compression benefits of pruning deteriorate or even vanish in ultra-low precision DNNs. This is due to (i) the unfavorable tradeoff between the number of bits needed to store a weight (which reduces with lower precision) and the number of bits needed to encode an index (which remains unchanged), and (ii) the lower sparsity levels that are achievable at lower precisions.We propose Seprox, a new compression scheme that overcomes the aforementioned challenges by exploiting two key observations about ultra-low precision DNNs. First, with lower precision, fewer weight values are possible, leading to increased incidence of frequently-occurring weights and weight sequences. Second, some weight values occur rarely and can be eliminated by replacing them with similar values. Leveraging these insights, Seprox encodes frequently-occurring weight sequences (as opposed to individual weights) while using the eliminated weight values to encode them, thereby avoiding indexing overheads and achieving higher compression. Additionally, Seprox uses approximation techniques to increase the frequencies of the encoded sequences. Across six ultralow precision DNNs trained on the Cifar10 and ImageNet datasets, Seprox achieves model compressions, energy improvements and speed-ups of up to 35.2%, 14.8% and 18.2% respectively.","PeriodicalId":367046,"journal":{"name":"Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115034310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Session details: Analyzing Reliability, Defects and Patterning 会议细节:分析可靠性，缺陷和模式

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design Pub Date : 2022-10-30 DOI: 10.1145/3578433

Gaurav Rajavendra Reddy, Kostas Adam

引用次数: 0

Session details: New Frontier in Verification Technology 会议详情:验证技术的新前沿

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design Pub Date : 2022-10-30 DOI: 10.1145/3578434

Jyotirmoy Vinay, Zahra Ghodsi

引用次数: 0

Applying GNNs to Timing Estimation at RTL GNNs在RTL定时估计中的应用

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design Pub Date : 2022-10-30 DOI: 10.1145/3508352.3561095

Daniela Sánchez Lopera, W. Ecker

{"title":"Applying GNNs to Timing Estimation at RTL","authors":"Daniela Sánchez Lopera, W. Ecker","doi":"10.1145/3508352.3561095","DOIUrl":"https://doi.org/10.1145/3508352.3561095","url":null,"abstract":"In the Electronic Design Automation (EDA) flow, signoff checks, such as timing analysis, are performed only after physical synthesis. Encountered timing violations cause re-iterations of the design flow. Hence, timing estimations at initial design stages, such as Register Transfer Level (RTL), would increase the quality of the results and lower the flow iterations. Machine learning has been used to estimate the timing behavior of chip components. However, existing solutions map EDA objects to Euclidean data without considering that EDA objects are represented naturally as graphs. Recent advances in Graph Neural Networks (GNNs) motivate the mapping from EDA objects to graphs for design metric prediction tasks at different stages. This paper maps RTL designs to directed, featured graphs with multidimensional node and edge features. These are the input to GNNs for estimating component delays and slews. An in-house hardware generation framework and open-source EDA tools for ASIC synthesis are employed for collecting training data. Experiments over unseen circuits show that GNN-based models are promising for timing estimation, even when the features come from early RTL implementations. Based on estimated delays, critical areas of the design can be detected, and proper RTL micro-architectures can be chosen without running long design iterations.","PeriodicalId":367046,"journal":{"name":"Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125622643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Gzippo

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design Pub Date : 2022-10-30 DOI: 10.1145/3508352.3549372

Xing Li, Rachata Ausavarungnirun, Xiao Liu, Xueyuan Liu, Xuan Zhang, Heng Lu, Zhuoran Song, Naifeng Jing, Xiaoyao Liang

引用次数: 1

Session details: Architectures and Methodologies for Advanced Hardware Security 会议细节:高级硬件安全的体系结构和方法

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design Pub Date : 2022-10-30 DOI: 10.1145/3578459

Amin Rezaei, Gang Qu

引用次数: 0

WaferHSL WaferHSL

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design Pub Date : 2022-10-30 DOI: 10.1145/3508352.3549466

Qijing Wang, Martin D. F. Wong

{"title":"WaferHSL","authors":"Qijing Wang, Martin D. F. Wong","doi":"10.1145/3508352.3549466","DOIUrl":"https://doi.org/10.1145/3508352.3549466","url":null,"abstract":"As the demand for semiconductor products increases and the integrated circuits (IC) processes become more and more complex, wafer failure pattern classification is gaining more attention from manufacturers and researchers to improve yield. To further cope with the real-world scenario that there are only very limited labeled data and without any unlabeled data in the early manufacturing stage of new products, this work proposes an efficient human-like staged learning framework for wafer failure pattern classification named WaferHSL. Inspired by human’s knowledge acquisition process, a mutually reinforcing task fusion scheme is designed for guiding the deep learning model to simultaneously establish the knowledge of spatial relationships, geometry properties and semantics. Furthermore, a progressive stage controller is deployed to partition and control the learning process, so as to enable human-like progressive advancement in the model. Experimental results show that with only 10% labeled samples and no unlabeled samples, WaferHSL can achieve better results than previous SOTA methods trained with 60% labeled samples and a large number of unlabeled samples, while the improvement is even more significant when using the same size of labeled training set.","PeriodicalId":367046,"journal":{"name":"Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121540572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Session details: Special Session: Making ML Reliable: From Devices to Systems to Software 特别会议:使机器学习可靠:从设备到系统再到软件

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design Pub Date : 2022-10-30 DOI: 10.1145/3578479

K. Chakrabarty, P. Pande

引用次数: 0

Session details: On Automating Heterogeneous Designs (Virtual) 会议细节:异构设计自动化(虚拟)

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design Pub Date : 2022-10-30 DOI: 10.1145/3578465

Haocheng Li

引用次数: 0