Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design最新文献

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ASPPLN
Weihua Xiao, Weikang Qian
{"title":"ASPPLN","authors":"Weihua Xiao, Weikang Qian","doi":"10.1145/3508352.3549456","DOIUrl":"https://doi.org/10.1145/3508352.3549456","url":null,"abstract":"Probability propagation is an important task used in logic network analysis, which propagates signal probabilities from its primary inputs to its primary outputs. It has many applications such as power estimation, reliability analysis, and error analysis for approximate circuits. Existing methods for the task can be divided into two categories: simulation-based and probability-based methods. However, most of them suffer from low accuracy or bad scalability. In this work, we propose ASPPLN, a method for accelerated symbolic probability propagation in logic network, which has a linear complexity with the network size. We first introduce a new definition in a graph called redundant input and take advantage of it to simplify the propagation process without losing accuracy. Then, a technique called symbol limitation is proposed to limit the complexity of each node’s propagation according to the partial probability significances of the symbols. The experimental results showed that compared to the existing methods, ASPPLN improves the estimation accuracy of switching activity by up to 24.70%, while it also has a speedup of up to 29×.","PeriodicalId":367046,"journal":{"name":"Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126367567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Quantum Machine Learning Applications in High-Energy Physics 量子机器学习在高能物理中的应用
Andrea Delgado, Kathleen E. Hamilton
{"title":"Quantum Machine Learning Applications in High-Energy Physics","authors":"Andrea Delgado, Kathleen E. Hamilton","doi":"10.1145/3508352.3561114","DOIUrl":"https://doi.org/10.1145/3508352.3561114","url":null,"abstract":"Some of the most significant achievements of the modern era of particle physics, such as the discovery of the Higgs boson, have been made possible by the tremendous effort in building and operating large-scale experiments like the Large Hadron Collider or the Tevatron. In these facilities, the ultimate theory to describe matter at the most fundamental level is constantly probed and verified. These experiments often produce large amounts of data that require storing, processing, and analysis techniques that continually push the limits of traditional information processing schemes. Thus, the High-Energy Physics (HEP) field has benefited from advancements in information processing and the development of algorithms and tools for large datasets. More recently, quantum computing applications have been investigated to understand how the community can benefit from the advantages of quantum information science. Nonetheless, to unleash the full potential of quantum computing, there is a need to understand the quantum behavior and, thus, scale up current algorithms beyond what can be simulated in classical processors. In this work, we explore potential applications of quantum machine learning to data analysis tasks in HEP and how to overcome the limitations of algorithms targeted for Noisy Intermediate-Scale Quantum (NISQ) devices.","PeriodicalId":367046,"journal":{"name":"Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131443707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Session details: Designing DNN Accelerators 会议细节:设计DNN加速器
Elliott Delaye, Yiyu Shi
{"title":"Session details: Designing DNN Accelerators","authors":"Elliott Delaye, Yiyu Shi","doi":"10.1145/3578437","DOIUrl":"https://doi.org/10.1145/3578437","url":null,"abstract":"","PeriodicalId":367046,"journal":{"name":"Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design","volume":"47 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131623627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Session details: Democratizing Design Automation with Open-Source Tools: Perspectives, Opportunities, and Challenges 会议细节:使用开源工具实现设计自动化的民主化:前景、机遇和挑战
Antonino Tumeo
{"title":"Session details: Democratizing Design Automation with Open-Source Tools: Perspectives, Opportunities, and Challenges","authors":"Antonino Tumeo","doi":"10.1145/3578430","DOIUrl":"https://doi.org/10.1145/3578430","url":null,"abstract":"","PeriodicalId":367046,"journal":{"name":"Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131944931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
FastStamp
Shehzeen Samarah Hussain, Nojan Sheybani, Paarth Neekhara, Xinqiao Zhang, J. Duarte, F. Koushanfar
{"title":"FastStamp","authors":"Shehzeen Samarah Hussain, Nojan Sheybani, Paarth Neekhara, Xinqiao Zhang, J. Duarte, F. Koushanfar","doi":"10.1145/3508352.3549357","DOIUrl":"https://doi.org/10.1145/3508352.3549357","url":null,"abstract":"Steganography and digital watermarking are the tasks of hiding recoverable data in image pixels. Deep neural network (DNN) based image steganography and watermarking techniques are quickly replacing traditional hand-engineered pipelines. DNN based watermarking techniques have drastically improved the message capacity, imperceptibility and robustness of the embedded watermarks. However, this improvement comes at the cost of increased computational overhead of the watermark encoder neural network. In this work, we design the first accelerator platform FastStamp to perform DNN based steganography and digital watermarking of images on hardware. We first propose a parameter efficient DNN model for embedding recoverable bit-strings in image pixels. Our proposed model can match the success metrics of prior state-of-the-art DNN based watermarking methods while being significantly faster and lighter in terms of memory footprint. We then design an FPGA based accelerator framework to further improve the model throughput and power consumption by leveraging data parallelism and customized computation paths. FastStamp allows embedding hardware signatures into images to establish media authenticity and ownership of digital media. Our best design achieves 68× faster inference as compared to GPU implementations of prior DNN based watermark encoder while consuming less power.","PeriodicalId":367046,"journal":{"name":"Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122028160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
MCQA MCQA
Sunghye Park, Dohun Kim, Jae-Yoon Sim, Seokhyeong Kang
{"title":"MCQA","authors":"Sunghye Park, Dohun Kim, Jae-Yoon Sim, Seokhyeong Kang","doi":"10.1145/3508352.3549462","DOIUrl":"https://doi.org/10.1145/3508352.3549462","url":null,"abstract":"In response to the rapid development of quantum processors, quantum software must be advanced by considering the actual hardware limitations. Among the various design automation problems in quantum computing, qubit allocation modifies the input circuit to match the hardware topology constraints. In this work, we present an effective heuristic approach for qubit allocation that considers not only the hardware topology but also other constraints for near-fault-tolerant quantum computing (near-FTQC). We propose a practical methodology to find an effective initial mapping to reduce both the number of gates and circuit latency. We then perform dynamic scheduling to maximize the number of gates executed in parallel in the main mapping phase. Our experimental results with a Surface-17 processor confirmed a substantial reduction in the number of gates, latency, and runtime by 58%, 28%, and 99%, respectively, compared with the previous method [18]. Moreover, our mapping method is scalable and has a linear time complexity with respect to the number of gates.","PeriodicalId":367046,"journal":{"name":"Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127265736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Session details: Hardware Security: Attacks and Countermeasures (Virtual) 硬件安全:攻击与对策(虚拟)
J. Knechtel, L. Batina
{"title":"Session details: Hardware Security: Attacks and Countermeasures (Virtual)","authors":"J. Knechtel, L. Batina","doi":"10.1145/3578445","DOIUrl":"https://doi.org/10.1145/3578445","url":null,"abstract":"","PeriodicalId":367046,"journal":{"name":"Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125030223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Session details: Design for Low Energy, Low Resource, but High Quality 会议细节:低能量,低资源,但高质量的设计
Ravikumar V. Chakaravarthy, Cong Hao
{"title":"Session details: Design for Low Energy, Low Resource, but High Quality","authors":"Ravikumar V. Chakaravarthy, Cong Hao","doi":"10.1145/3578474","DOIUrl":"https://doi.org/10.1145/3578474","url":null,"abstract":"","PeriodicalId":367046,"journal":{"name":"Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design","volume":"443 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122153615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Re 2 fresh 新鲜的
Hyein Shin, Myeonggu Kang, Lee-Sup Kim
{"title":"Re\u0000 <sup>2</sup>\u0000 fresh","authors":"Hyein Shin, Myeonggu Kang, Lee-Sup Kim","doi":"10.1145/3508352.3549345","DOIUrl":"https://doi.org/10.1145/3508352.3549345","url":null,"abstract":"A severe read disturbance problem degrades the inference accuracy of a resistive RAM (ReRAM) based deep neural network (DNN) accelerator. Refresh, which reprograms the ReRAM cells, is the most obvious solution for the problem, but programming ReRAM consumes huge energy. To address the issue, we first analyze the resistance drift pattern of each conductance state and the actual read stress applied to the ReRAM array by considering the characteristics of ReRAM-based DNN accelerators. Based on the analysis, we cluster ReRAM cells into a few groups for each layer of DNN and generate a proper refresh cycle for each group in the offline phase. The individual refresh cycles reduce energy consumption by reducing the number of unnecessary refresh operations. In the online phase, the refresh controller selectively launches refresh operations according to the generated refresh cycles. ReRAM cells are selectively refreshed by minimally modifying the conventional structure of the ReRAM-based DNN accelerator. The proposed work successfully resolves the read disturbance problem by reducing 97% of the energy consumption for the refresh operation while preserving inference accuracy.","PeriodicalId":367046,"journal":{"name":"Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122297549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Session details: Compiler and System-Level Techniques for Efficient Machine Learning 会议细节:高效机器学习的编译器和系统级技术
S. Parameswaran, Martin Rapp
{"title":"Session details: Compiler and System-Level Techniques for Efficient Machine Learning","authors":"S. Parameswaran, Martin Rapp","doi":"10.1145/3578427","DOIUrl":"https://doi.org/10.1145/3578427","url":null,"abstract":"","PeriodicalId":367046,"journal":{"name":"Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design","volume":"284 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114106907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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