Jorge N. Moreno, Osvaldo Gonzalez, Rafael Vega, R. Palomera, M. Jimenez
{"title":"Emulating an Agilent™ 4142 on a Keithley™ 2600 series Source Measurement Unit","authors":"Jorge N. Moreno, Osvaldo Gonzalez, Rafael Vega, R. Palomera, M. Jimenez","doi":"10.1109/LATW.2010.5550376","DOIUrl":"https://doi.org/10.1109/LATW.2010.5550376","url":null,"abstract":"This paper presents the development of an emulation software downloadable onto a Keithley 2600 series SMU, allowing it to emulate the functionality of an Agilent 4142 unit. The emulation system was developed as a series of scripts written in Lua, the native scripting language for Keithley 2600 series. A two-folded validation procedure is presented to ensure the emulated commands perform as the original commands. Results show a nearly perfect match between both results, highlighting the validity of the developed emulation system.","PeriodicalId":358177,"journal":{"name":"2010 11th Latin American Test Workshop","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123310616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hanno Hantson, J. Raik, M. Jenihhin, A. Chepurov, R. Ubar, G. D. Guglielmo, F. Fummi
{"title":"Mutation analysis with high-level decision diagrams","authors":"Hanno Hantson, J. Raik, M. Jenihhin, A. Chepurov, R. Ubar, G. D. Guglielmo, F. Fummi","doi":"10.1109/LATW.2010.5550336","DOIUrl":"https://doi.org/10.1109/LATW.2010.5550336","url":null,"abstract":"The paper presents a new tool for mutation analysis using the system model of high-level decision diagrams (HLDD). The tool is integrated into the APRICOT verification environment. It is based on HLDD simulation and graph perturbation. A strategy that relies on a restricted set of five key mutation operators is developed in order to speed up the mutation analysis. Experiments on several ITC99 benchmarks and an industrial example show the feasibility of the mutation analysis approach.","PeriodicalId":358177,"journal":{"name":"2010 11th Latin American Test Workshop","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116439961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Variability-aware physical design techniques","authors":"G. Wilke, R. Reis","doi":"10.1109/LATW.2010.5550347","DOIUrl":"https://doi.org/10.1109/LATW.2010.5550347","url":null,"abstract":"Dealing with process and environmental variability became a great challenge for IC designers in the latest technology nodes. Digital circuits are designed in such a way that timing and power constraints are respected with minimum resource usage, to do that tight power and timing margins are desired. If process and environmental variability are not accounted during the design stage power and timing margins may not be sufficient to accommodate variability effect. To guarantee robust operation physical design algorithms must account for the variability effect. This presentation gives an overview of some of the available techniques for designing variation tolerant circuits. Techniques for robust clock distribution and routing will be approached.","PeriodicalId":358177,"journal":{"name":"2010 11th Latin American Test Workshop","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129956716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Marinho, P. Maciel, E. Sousa, Teresa M. Maciel, E. Andrade
{"title":"Performance evaluation model for test process","authors":"M. Marinho, P. Maciel, E. Sousa, Teresa M. Maciel, E. Andrade","doi":"10.1109/LATW.2010.5550380","DOIUrl":"https://doi.org/10.1109/LATW.2010.5550380","url":null,"abstract":"The interest in software testing activities is on the high side these days, but a sound planning is necessary so that all tests are realized successfully. The objective of test planning is to plan testing activities to be executed throughout the life-cycle of the project. In this article, concepts related to testing processes are mapped in Stochastic Petri Nets(SPN) which provides a formal representation for measures used in performance analysis.","PeriodicalId":358177,"journal":{"name":"2010 11th Latin American Test Workshop","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132941754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On improving real-time observability for in-system post-silicon debug","authors":"N. Nicolici","doi":"10.1109/LATW.2010.5550350","DOIUrl":"https://doi.org/10.1109/LATW.2010.5550350","url":null,"abstract":"To identify design errors that escape pre-silicon verification, post-silicon debug is becoming an important step in the implementation flow of digital circuits. It is concerned with identifying design errors that escape to silicon. While commonly used in practice, it has received less research focus when compared to its complementary problem of manufacturing test, which is focused on screening for fabrication defects. We provide the background and summarize some recent research that addresses the emerging challenges.","PeriodicalId":358177,"journal":{"name":"2010 11th Latin American Test Workshop","volume":"37 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133585223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Manufacturers to end-users tools for radiations induced reliability issues in electronic devices","authors":"F. Wrobel","doi":"10.1109/LATW.2010.5550351","DOIUrl":"https://doi.org/10.1109/LATW.2010.5550351","url":null,"abstract":"Natural radiations induced failures in microelectronics has first been a real concern for space and avionic communities. Due to device integration this is now an issue for all commercial applications even at ground level. As an example, single event transients and soft errors are an actual concern. Natural radioactivity also contributes to this issue, especially at ground and underground levels. Simulation tools are very useful to establish the transient current shapes and to evaluate the soft error rate. This kind of code can be validated thanks to accelerated tests under beam and/or accelerated test in natural environment (i.e. in altitude).","PeriodicalId":358177,"journal":{"name":"2010 11th Latin American Test Workshop","volume":"186 14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130173035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Gonçalves, E. L. Schneider, R. V. Henriques, M. Lubaszewski, Jefferson Luiz Bosa, P. Engel
{"title":"Fault prediction in electrical valves using temporal Kohonen maps","authors":"L. Gonçalves, E. L. Schneider, R. V. Henriques, M. Lubaszewski, Jefferson Luiz Bosa, P. Engel","doi":"10.1109/LATW.2010.5550338","DOIUrl":"https://doi.org/10.1109/LATW.2010.5550338","url":null,"abstract":"This paper presents a proactive maintenance scheme for the prediction of faults in electrical valves. In our case study, these valves are used for controlling the oil flow in a distribution network. A system implements temporal self-organizing maps for the prediction of faults. These faults lead to deviations either on torque, on the valve end position or on opening/closing time. For fault prediction, one map is trained using data from a mathematical model devised for the electrical valve. The training is performed by fault injection based on three parameter deviations over this same mathematical model. The map learns the energies of the torque and the position that are computed using the wavelet packet transform. Once the map is trained, the system is ready for on-line monitoring of the valve. During the on-line testing phase, the system computes the Euclidean distance and the activation of data series. The biggest activation determines which is the winner neuron of the map for one data series. The obtained results demonstrate a new solution for prediction behavior of these valves.","PeriodicalId":358177,"journal":{"name":"2010 11th Latin American Test Workshop","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134090332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Azambuja, Fernando Sousa, Lucas Rosa, F. Kastensmidt
{"title":"The limitations of software signature and basic block sizing in soft error fault coverage","authors":"J. Azambuja, Fernando Sousa, Lucas Rosa, F. Kastensmidt","doi":"10.1109/LATW.2010.5550346","DOIUrl":"https://doi.org/10.1109/LATW.2010.5550346","url":null,"abstract":"This paper presents a detailed analysis of the efficiency of software-only techniques to mitigate SEU and SET in microprocessors. A set of well-known rules is presented and implemented automatically to transform an unprotected program into a hardened one. SEU and SET are injected in all sensitive areas of MIPS-based microprocessor architecture. The efficiency of each rule and a combination of them are tested. Experimental results show the limitations of the control-flow techniques in detecting the majority of SEU and SET faults, even when different basic block sizes are evaluated. A further analysis on the undetected faults with control flow effect is done and five causes are explained. The conclusions can lead designers in developing more efficient techniques to detect these types of faults.","PeriodicalId":358177,"journal":{"name":"2010 11th Latin American Test Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128901944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. M. Espinosa-Duran, V. Trujillo-Olaya, Jaime Velasco-Medina, R. Velazco
{"title":"Bit-flip injection strategies for FSMs modeled in VHDL behavioral level","authors":"J. M. Espinosa-Duran, V. Trujillo-Olaya, Jaime Velasco-Medina, R. Velazco","doi":"10.1109/LATW.2010.5550340","DOIUrl":"https://doi.org/10.1109/LATW.2010.5550340","url":null,"abstract":"This paper presents two strategies to inject bit-flips in FSMs modeled in VHDL behavioral level. The dependability validation to SEUs or MEUs into the FSM flip flops is carried out by means of minor modifications on the VHDL description. The simulation results show that the proposed strategies have a low area overhead, allow synchronous and asynchronous fault injection and are very suitable to carry out the dependability validation step on FSMs.","PeriodicalId":358177,"journal":{"name":"2010 11th Latin American Test Workshop","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122046557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Avendaño, Pablo Fuentes, Victor Castillo, Constanza Garcia, N. Domínguez
{"title":"Reliability and safety of medical equipment by use of calibration and certification instruments","authors":"G. Avendaño, Pablo Fuentes, Victor Castillo, Constanza Garcia, N. Domínguez","doi":"10.1109/LATW.2010.5550349","DOIUrl":"https://doi.org/10.1109/LATW.2010.5550349","url":null,"abstract":"The tutorial refers to the need for all equipment and facilities related to human health must be adequately verified in calibration and functionality, as any calibration error, indicating graphic display or measured performance parameters can become a source of serious problems for patients. Therefore there is a line of important work in Biomedical Engineering, dedicated to the creation of complementary technology to certify and eventually help calibrate Biomedical technology that has direct or indirect relationship with patients. The work show some important iatrogenic effects and our developments in this field","PeriodicalId":358177,"journal":{"name":"2010 11th Latin American Test Workshop","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128894382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}