在VHDL行为层面建模的FSMs的位翻转注入策略

2010 11th Latin American Test Workshop Pub Date : 2010-03-28 DOI:10.1109/LATW.2010.5550340

J. M. Espinosa-Duran, V. Trujillo-Olaya, Jaime Velasco-Medina, R. Velazco

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引用次数: 1

摘要

本文提出了在VHDL行为层建模的FSMs中注入位翻转的两种策略。通过对VHDL描述的微小修改，实现了对FSM触发器中seu或meu的可靠性验证。仿真结果表明，该策略具有面积开销小、允许同步和异步故障注入的特点，非常适合在fsm上进行可靠性验证。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Bit-flip injection strategies for FSMs modeled in VHDL behavioral level

This paper presents two strategies to inject bit-flips in FSMs modeled in VHDL behavioral level. The dependability validation to SEUs or MEUs into the FSM flip flops is carried out by means of minor modifications on the VHDL description. The simulation results show that the proposed strategies have a low area overhead, allow synchronous and asynchronous fault injection and are very suitable to carry out the dependability validation step on FSMs.

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2010 11th Latin American Test Workshop

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