Variability-aware physical design techniques

Abstract

Dealing with process and environmental variability became a great challenge for IC designers in the latest technology nodes. Digital circuits are designed in such a way that timing and power constraints are respected with minimum resource usage, to do that tight power and timing margins are desired. If process and environmental variability are not accounted during the design stage power and timing margins may not be sufficient to accommodate variability effect. To guarantee robust operation physical design algorithms must account for the variability effect. This presentation gives an overview of some of the available techniques for designing variation tolerant circuits. Techniques for robust clock distribution and routing will be approached.