Marcos Herve, Pedro Almeida, F. Kastensmidt, É. Cota, M. Lubaszewski
{"title":"Concurrent test of Network-on-Chip interconnects and routers","authors":"Marcos Herve, Pedro Almeida, F. Kastensmidt, É. Cota, M. Lubaszewski","doi":"10.1109/LATW.2010.5550355","DOIUrl":"https://doi.org/10.1109/LATW.2010.5550355","url":null,"abstract":"In this work, a functional-based test method is presented that integrates the test of Network-on-Chip interconnects and routers. The proposed approach is scalable to any size of network. Experimental results show that fault coverage can reach up to 100% of interconnect faults and 92.75% of router faults, with yet affordable test sequence lengths.","PeriodicalId":358177,"journal":{"name":"2010 11th Latin American Test Workshop","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125156861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Lavratti, A. R. Pinto, D. Prestes, L. Bolzani, Fabian Vargas, C. Montez
{"title":"Towards a transmission power self-optimization in reliable Wireless Sensor Networks","authors":"F. Lavratti, A. R. Pinto, D. Prestes, L. Bolzani, Fabian Vargas, C. Montez","doi":"10.1109/LATW.2010.5550356","DOIUrl":"https://doi.org/10.1109/LATW.2010.5550356","url":null,"abstract":"Wireless Sensor Networks (WSNs) can be used to monitor hazardous and inaccessible areas. The WSN is composed of several nodes each provided with its separated power supply, e.g. battery. Working in hardly accessible places it is preferable to assure the adoption of the minimum transmission power in order to prolong as much as possible the WSN's lifetime. Though, we have to keep in mind that the reliability of the data transmitted represents a crucial requirement. Therefore, power optimization and reliability have become the most important concerns when dealing with modern systems based on WSN. In this context, we propose a new algorithm able to guarantee an equally high Quality of Service (QoS), concentrating on the WSN's Efficiency (Ef), while optimizing the transmission power necessary for data communication. Thus, the main idea behind our approach is to reach a trade-off between Ef and energy consumption in an environment with inherent noise.","PeriodicalId":358177,"journal":{"name":"2010 11th Latin American Test Workshop","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132810946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Heterogeneous integration: Beyond CMOS – coping with variability at the end of the CMOS roadmap","authors":"S. Bampi","doi":"10.1109/LATW.2010.5550352","DOIUrl":"https://doi.org/10.1109/LATW.2010.5550352","url":null,"abstract":"By 2020 it is very likely that nano-CMOS will reach the end of the scaling roadmap. Current 32nm CMOS production technology already is hampered by large variations in electrical parameters, with impacts on performance predictability, power consumption limitations and design closure for complex systems. Heterogeneous integration is the roadmap to lower cost and yet more advanced and innovative functionalities on silicon, with new and more manageable challenges. There will be no end nor a definite demise of silicon technology. While there are uncertainties as to what will be the show-stoppers for the down-scaling of nano-CMOS, there is a large number of transitional and compatible to CMOS technologies that will be more important than just 2-D scaling. This talk discusses variability among other limitations that bring the end of 2-D scaling and also proposes a likely scenario for hardware technology evolution and related challenges for integrating systems in the next 20 years. The scenario beyond the end of the roadmap is drawn, in which heterogeneous integration at the device level as well as at the system level will bring new frontiers to the ULSI era of tera-scale integration. Transitional technologies like 3-D integration by through-silicon vias, carbon-based electron devices, and even magnetic materials devices will co-exist and be built upon a basic CMOS-like technology platform.","PeriodicalId":358177,"journal":{"name":"2010 11th Latin American Test Workshop","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117130882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Pous, F. Azaïs, L. Latorre, P. Nouet, J. Rivoir
{"title":"Experiments on the analysis of phase/frequency-modulated RF signals using digital tester channels","authors":"N. Pous, F. Azaïs, L. Latorre, P. Nouet, J. Rivoir","doi":"10.1109/LATW.2010.5550370","DOIUrl":"https://doi.org/10.1109/LATW.2010.5550370","url":null,"abstract":"This paper presents experiments around the analysis of phase/frequency-modulated signals using digital ATE channels. Based on the concept of zero-crossing detection, the proposed technique relies on the sampling of the analog/RF signal through a 1-bit comparator and the post-processing of the resulting bit stream. Coherent under sampling is used to extend the application range of the method, allowing the analysis of high-speed analog signals using standard test equipment operating with a limited sampling frequency. Simulation results show the viability of the technique. Hardware experiments are presented, which are in good agreement with simulation results.","PeriodicalId":358177,"journal":{"name":"2010 11th Latin American Test Workshop","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131071844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Muhammad Mudassar Nisar, Jayaram Natarajan, A. Chatterjee
{"title":"Dynamic power modulation in baseband OFDM signal processor using application driven metrics: Image transmission and processing","authors":"Muhammad Mudassar Nisar, Jayaram Natarajan, A. Chatterjee","doi":"10.1109/LATW.2010.5550374","DOIUrl":"https://doi.org/10.1109/LATW.2010.5550374","url":null,"abstract":"In this research we study how power can be saved in the baseband processor of an OFDM transceiver from the knowledge of an end application to which the transmitted or received data is applied. The specific applications that we study are image and video transmission across a wireless link. It is assumed that edge detection (image) and object tracking (video) is to be performed on the received data. Power is saved by reducing the wordlength of computation in the filters and FFT functions of the baseband processor and simultaneously reducing the supply voltage. Power modulation is done on the basis of closed-loop feedback control using a control law that continuously \"tunes\" the baseband processor for minimum power using the wireless channel quality, the image/video quality and the current quality of baseband signal processing as input parameters. It is assumed that the image/video quality metric is computed by the image acquisition system and transmitted along with data.","PeriodicalId":358177,"journal":{"name":"2010 11th Latin American Test Workshop","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115830969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Diversity TMR: Proof of concept in a mixed-signal case","authors":"G. Borges, L. Gonçalves, T. Balen, M. Lubaszewski","doi":"10.1109/LATW.2010.5550343","DOIUrl":"https://doi.org/10.1109/LATW.2010.5550343","url":null,"abstract":"In this paper a design diversity fault tolerance technique is applied to a mixed-signal (MS) system. Three different implementations of a second order low-pass filter (which perform the same transfer function) associated to a majority voter are used to build the TMR scheme. The whole system is prototyped by using a programmable mixed-signal device. Some functional faults are injected into the circuit blocks and practical measurements are made on the prototyped system. Results show that the design diversity TMR is a feasible technique that can increase reliability of some classes of state-of-art MS circuits.","PeriodicalId":358177,"journal":{"name":"2010 11th Latin American Test Workshop","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115076017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"BICS-based March test for resistive-open defect detection in SRAMs","authors":"R. Chipana, L. Bolzani, F. Vargas","doi":"10.1109/LATW.2010.5550342","DOIUrl":"https://doi.org/10.1109/LATW.2010.5550342","url":null,"abstract":"Nowadays, embedded Static Random Memories (SRAMs) can occupy a significant portion of the chip area and contain hundreds of millions of transistors. Due to technology scaling, functional fault models traditionally applied in SRAMs' testing have become insufficient to correctly reproduce the effects caused by some defects generated during the manufacturing process. In this paper, we investigate the possibility to use Built-In Current Sensors (BICSs) in combination with an optimized March algorithm to detect static faults associated to resistive-open defects. Experimental results obtained throughout electrical simulations validate the proposed technique demonstrating its viability and effectiveness.","PeriodicalId":358177,"journal":{"name":"2010 11th Latin American Test Workshop","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129429888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ruthiano S. Munaretti, B. Fiss, T. Weber, S. Cechin
{"title":"Experimental dependability assessment using a faultload specification tool","authors":"Ruthiano S. Munaretti, B. Fiss, T. Weber, S. Cechin","doi":"10.1109/LATW.2010.5550373","DOIUrl":"https://doi.org/10.1109/LATW.2010.5550373","url":null,"abstract":"Use of two or more fault injection tools in a test campaign enriches the scenario obtained from a test execution. Faultloads represent the main input for these tools but their specification mechanisms lack usability and expressiveness. This paper presents a full test scenario featuring the use of jFaultload, which applies Java for the specification of fault-loads and translates them to specific formats that are appropriate to each available fault injector. FIRMAMENT, a fault injector for communication systems, was integrated in the environment and completes the test scenario. The service under test used to demonstrate the usability and expressiveness of our solution is a video streaming session using RTP Protocol.","PeriodicalId":358177,"journal":{"name":"2010 11th Latin American Test Workshop","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116875973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On Comparing and Complementing two MBT approaches","authors":"M. Cristiá, V. A. S. Júnior, N. Vijaykumar","doi":"10.1109/LATW.2010.5550339","DOIUrl":"https://doi.org/10.1109/LATW.2010.5550339","url":null,"abstract":"At INPE1 researchers and software engineers have been using Statechart-based testing for some time to test on-board satellite software. On the other hand, a group of researchers at CIFASIS2 and Flowgate Consulting have been applying Z-based testing for unit testing. Both groups started to compare their approaches and tools a year ago. What started as a comparison to share ideas and results, is now turning into the realization that actually both techniques complement and benefit from each other, yielding a more effective and wider Model-Based Testing (MBT) approach. In this paper we present the results obtained so far in comparing and complementing these two MBT techniques.","PeriodicalId":358177,"journal":{"name":"2010 11th Latin American Test Workshop","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123513906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An algorithm for diagnostic fault simulation","authors":"Yu Zhang, V. Agrawal","doi":"10.1109/LATW.2010.5550345","DOIUrl":"https://doi.org/10.1109/LATW.2010.5550345","url":null,"abstract":"In diagnostic testing faults detectable by test vectors are partitioned into groups. This partitioning is such that a fault is distinguishable from faults in all other groups, but is indistinguishable from those in its own group. Diagnostic fault coverage (DC) is defined as the number of fault groups divided by the total number of faults. We present a new diagnostic fault simulation algorithm that determines the DC of given test vectors and produces a fault dictionary. For each vector, we begin with detected fault list at each primary output obtained from a convetional fault simulator. For the vector being simulated each fault is assigned a detection index that uniquely specifies its detection status at all primary outputs. Fault list is then partitioned. Faults with different detection index are distinguished by the simulated vector and are kept in separate groups. Any fault in a group by itself is dropped from further simulation with subsequent vectors for which its detection index remains unknown (X). After simulation of each vector, the cumulative DC is obtained by counting the fault groups. Fault dictionary syndrome for a fault is the array of its detection indexes.","PeriodicalId":358177,"journal":{"name":"2010 11th Latin American Test Workshop","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124549614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}