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2006 International Symposium on VLSI Design, Automation and Test最新文献

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An Efficient Field-Partition Based Code Compression and Its Pipelined Decompression System 一种高效的基于域划分的代码压缩及其流水线解压缩系统
2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258133
Y. Jeang, Yong Lin
{"title":"An Efficient Field-Partition Based Code Compression and Its Pipelined Decompression System","authors":"Y. Jeang, Yong Lin","doi":"10.1109/VDAT.2006.258133","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258133","url":null,"abstract":"A field partition based instruction compression/decompression system for ARM series architecture is proposed. Due to a high degree of repetition in the encoding of the specific fields of the instructions in a program, we could get a statistics of the appearances of each field in all instructions of a program. Depending on the statistics, we partition each instruction into three fields and compress each field using Huffman coding method. Experimental results show that our method is better than others with a 55% of average compression ratio. For decompression, single buffering, double buffering and pipeline techniques have been proposed. However, due to jump penalty, these techniques incur more delays in pipeline or have to stop and fill in the cache buffers. We proposed a pipeline with back-up for flushing technique that incurs no delay and without stopping due to jump. The average performance is increased about 10% to 60%","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116485427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Monolithic Class E SiGe Power Amplifier Design with Wideband High-Efficiency and Linearity 宽带、高效率、线性的单片E级SiGe功率放大器设计
2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258128
Donald Y. C. Lie, J. Popp, P. Lee, A. Yang, Jason Rowlando, Feipeng Wang, Donald Kimball
{"title":"Monolithic Class E SiGe Power Amplifier Design with Wideband High-Efficiency and Linearity","authors":"Donald Y. C. Lie, J. Popp, P. Lee, A. Yang, Jason Rowlando, Feipeng Wang, Donald Kimball","doi":"10.1109/VDAT.2006.258128","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258128","url":null,"abstract":"This paper discusses and compares the design of monolithic RF broadband class E SiGe power amplifiers (PAs) centered at 900MHz that are highly efficient and linear. It is found that high power-added-efficiency (~65%) can be achieved with PAs designed using either high-breakdown or high-fT SiGe transistors. The PAs designed with high-breakdown devices can provide ~3% better efficiency at higher supply voltages but with worse bias sensitivity, inferior broadband frequency response, and slightly lower gain than those designed with high-fT devices. However, the class E PAs designed using high-breakdown devices can be successfully linearized using an open-loop envelope tracking (ET) technique as their output spectra pass the stringent EDGE transmit mask with margins, achieving an overall system PAE of 44.4% that surpasses the ~30% PAE obtainable using commercial GaAs class AB PAs. These promising results indicate the feasibility of realizing true single-chip wireless transceivers with on-chip RF SiGe PAs for spectrally-efficient non-constant-envelope modulation schemes","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"424 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123096127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Hazard-Aware Performance Prediction for Automatic Instruction-Set Selection 自动指令集选择的危险感知性能预测
2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258123
P. Hallschmid, R. Saleh
{"title":"Hazard-Aware Performance Prediction for Automatic Instruction-Set Selection","authors":"P. Hallschmid, R. Saleh","doi":"10.1109/VDAT.2006.258123","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258123","url":null,"abstract":"Recent research in the area of application specific instruction set processors (ASIPs) has focused on the automatic selection of a custom instruction set based on a high level description of the application. Existing methods perform instruction selection under the assumption that data hazards can be ignored due to functional unit forwarding. This paper addresses data hazards in the ASIP flow when functional unit to functional unit forwarding is too expensive. This is accomplished by devising a \"hazard-aware\" predictor for measuring the impact of custom instructions on performance. Results show that our predictor reduces prediction error from 50% to 15% compared to the existing simple predictor and with a fraction of the run-time of rescheduling. When incorporated into an instruction enumeration and selection algorithm, our predictor reduces the total schedule length by as much as 8.4%","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"40 1-8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123379202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An All-Digital Duty Cycle Corrector 全数字占空比校正器
2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258158
Bo-Jiun Chen, Shao-Ku Kao, Shen-Iuan Liu
{"title":"An All-Digital Duty Cycle Corrector","authors":"Bo-Jiun Chen, Shao-Ku Kao, Shen-Iuan Liu","doi":"10.1109/VDAT.2006.258158","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258158","url":null,"abstract":"An all-digital 50% duty cycle corrector (DCC) is presented. The features of the proposed DCC include a wide operation frequency range, a wide input duty cycle range for the input clock, and a short locked time to recover the duty cycle of 50%. This digital DCC has been implemented in a 0.35mum 2P4M CMOS process. The acceptable duty cycle and frequency range of the input clock is 25%-75% and 250MHz-600MHz, respectively. The measured peak-peak jitter is 17.3ps at 600MHz. Besides, this DCC saves the power consumption by turning off a half delay line. Its power consumption is 16mW at 600MHz","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"466 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123020468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 6-b 1.3Gs/s A/D Converter with C-2C Switch-Capacitor Technique 基于C-2C开关电容技术的6b 1.3Gs/s A/D变换器
2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258136
Ying-Min Liao, Tai-Cheng Lee
{"title":"A 6-b 1.3Gs/s A/D Converter with C-2C Switch-Capacitor Technique","authors":"Ying-Min Liao, Tai-Cheng Lee","doi":"10.1109/VDAT.2006.258136","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258136","url":null,"abstract":"A 6-b 1.3-Gs/s pipelined successive-approximation analog-to-digital converter (ADC) is presented. Employing improved-MMS and C-2C architecture, the circuit operates in high speed and low power consumption. With open-loop architecture, the T/H circuit can work at a high conversion rate. The proposed architecture reduces the static power consumption by charge redistribution digital-to-analog converter (DAC) and lowers the accuracy requirement of the capacitor in the conventional successive-approximation (SA)-ADC by the C-2C architecture. Designed in a 0.18-mum technology, the ADC operates at 1.3-Gs/s clock rate while power dissipation is 196 mW. The FFT simulation result shows that the SNDR is 34 dB at 130-MHz input frequency and 1.3-Gs/s conversion rate","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128417029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Improving Single-Pass Redundancy Addition and Removal with Inconsistent Assignments 基于不一致赋值的单遍冗余添加和删除改进
2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258153
W. Lo, Yu-Liang Wu
{"title":"Improving Single-Pass Redundancy Addition and Removal with Inconsistent Assignments","authors":"W. Lo, Yu-Liang Wu","doi":"10.1109/VDAT.2006.258153","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258153","url":null,"abstract":"Redundancy addition and removal, also known as rewiring, is a building block of a wide range of circuit optimization applications. In this paper, we propose a novel improvement on the FIRE redundancy identification technique and augment the state-of-the-art rewiring scheme RAMFIRE with it. Our method increases the number of alternative wires identified by 10% and improves the runtime by nearly 20%. Optimization applications based on rewiring can take the advantage of this speed up and enhanced rewiring power","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128042752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
New LCD Display Technology for High Performance with Low Cost-Shared Pixel Rendering Display 新型LCD显示技术实现高性能、低成本的共享像素渲染显示
2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258113
C. Chien, A. Wang, Weber Chien
{"title":"New LCD Display Technology for High Performance with Low Cost-Shared Pixel Rendering Display","authors":"C. Chien, A. Wang, Weber Chien","doi":"10.1109/VDAT.2006.258113","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258113","url":null,"abstract":"Conventional displays often use a striped RGB pattern, but there exists some side-effect, such as sawtooth pattern, lower-yield rate and lower resolution/per area etc. Sitronix Technology Co. Ltd. are discovering alternative patterns, called SPRD, that could offer some new benefits. It combines the unique color filter and algorithm to perform the best display quality","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"269 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114423392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A CMOS Variable Gain Amplifier with DC Offset Calibration Loop for Wireless Communications 一种用于无线通信的带直流偏置校正环路的CMOS变增益放大器
2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258115
Zhih-Siou Cheng, J. Bor
{"title":"A CMOS Variable Gain Amplifier with DC Offset Calibration Loop for Wireless Communications","authors":"Zhih-Siou Cheng, J. Bor","doi":"10.1109/VDAT.2006.258115","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258115","url":null,"abstract":"A 64 dB gain range VGA with DC offset calibration loop is proposed in this work. This VGA adopts the degeneration type amplifier to vary voltage gain and uses the super-source-follower input stage to enhance the linearity. A digital-based DC offset calibration loop is also designed to solve the DC offset problem. An experimental chip is fabricated in 0.18 mum process. With 2 dB step, the gain error is less than 0.8 dB and the output DC offset is less than 100mV at maximum gain setting. The total power consumption is 11 mW","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116133529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A Self-Biased Current Source Based Power-On Reset Circuit for On-Chip Applications 一种基于自偏置电流源的芯片上电复位电路
2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258175
A. Katyal, N. Bansal
{"title":"A Self-Biased Current Source Based Power-On Reset Circuit for On-Chip Applications","authors":"A. Katyal, N. Bansal","doi":"10.1109/VDAT.2006.258175","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258175","url":null,"abstract":"Power-on reset circuits are available as discrete devices as well as on-chip solutions and are indispensable to initialize some critical nodes of analog and digital designs during power-on. In this paper, we present a power-on reset circuit specifically designed for on-chip applications. The mentioned POR circuit should meet certain design requirements necessary to be integrated on-chip, some of them being area-efficiency, power-efficiency, supply rise-time insensitivity and ambient temperature insensitivity. The circuit is implemented within a small area (60mum times 35mum) using the 2.5V tolerant MOSFETs of a 0.28mum CMOS technology. It has a maximum quiescent current consumption of 40muA and works over infinite range of supply rise-times and ambient temperature range of -40degC to 150degC","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123831427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 75MS/s Low Power Pipeline ADC with scalable Resolution 具有可扩展分辨率的75MS/s低功耗流水线ADC
2006 International Symposium on VLSI Design, Automation and Test Pub Date : 2006-04-26 DOI: 10.1109/VDAT.2006.258135
D. Muthers, R. Tielert
{"title":"A 75MS/s Low Power Pipeline ADC with scalable Resolution","authors":"D. Muthers, R. Tielert","doi":"10.1109/VDAT.2006.258135","DOIUrl":"https://doi.org/10.1109/VDAT.2006.258135","url":null,"abstract":"A low power pipeline ADC with selectable resolutions of 13bit and 11bit has been implemented. The maximum sampling rate is 75MS/s. In 13bit mode the power consumption is 49mW and the SINAD 67.4dB for a 0.5MHz signal. In 11 bit mode it consumes 26mW, the SINAD is 62.1dB for a 0.5MHz signal. The low power consumption has been achieved by omitting building blocks that are not absolutely essential for a pipeline ADC, like an active S&H or a common-mode regulation","PeriodicalId":356198,"journal":{"name":"2006 International Symposium on VLSI Design, Automation and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128985930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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