2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)最新文献

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Shared hardware accelerator architectures for heterogeneous MPSoCs 异构mpsoc的共享硬件加速器架构
Bouthaina Damak, M. Baklouti, S. Niar, M. Abid
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引用次数: 13
Flexible, ultra-low power sensor nodes through configurable finite state machines 灵活,超低功耗传感器节点通过可配置的有限状态机
J. P. Ramos, M. Verhelst
{"title":"Flexible, ultra-low power sensor nodes through configurable finite state machines","authors":"J. P. Ramos, M. Verhelst","doi":"10.1109/ReCoSoC.2013.6581533","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2013.6581533","url":null,"abstract":"Due to the recent popularity of context-sensitive applications, there is a growing need for reliable, long-lifetime ubiquitous sensor nodes. The severe energy-efficiency requirements of these energy-scarce devices require complementing traditional circuit-level energy saving techniques, with architecture-level methods. Traditional approaches such as exploiting parallelism have however limited impact in sensor node processors, due to their control-dominated and event-based, irregular data processing workload patterns. Executing event-based tasks in specialized finite state machines relieves the on-board microcontroller, however, at the penalty of reduced post-manufacturing configurability. An architecture proposal for configurable finite state machines assisting sensor node processors is presented, which allows saving energy through task off-load while maintaining system flexibility. Simulations demonstrate 46% energy savings when compared to a sensor node that executes tasks in a microcontroller. This gain comes at relatively minor area overhead.","PeriodicalId":354964,"journal":{"name":"2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132818400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Practical measurements of data path delays for IP authentication & integrity verification IP认证和完整性验证的数据路径延迟的实际测量
Ingrid Exurville, J. Fournier, J. Dutertre, B. Robisson, A. Tria
{"title":"Practical measurements of data path delays for IP authentication & integrity verification","authors":"Ingrid Exurville, J. Fournier, J. Dutertre, B. Robisson, A. Tria","doi":"10.1109/ReCoSoC.2013.6581551","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2013.6581551","url":null,"abstract":"This paper describes the results of the practical measurements done to determine the path delay associated with each bit of a hardware AES FPGA implementation using a clock glitch injection tool. We illustrate how the measured path delays can constitute a characteristic fingerprint of an Intellectuel Property (IP) and can be used to detect the insertion of hardware trojans. The influence of synthesis options and inter die variations on the measurements is also studied. Compared to trojan detection schemes based on path delay characterisations already proposed in the literature, our approach does not require any additional test circuit to be inserted in the IP. Moreover our results are based on practical measurements.","PeriodicalId":354964,"journal":{"name":"2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130512712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
The HeartBeat model: A platform abstraction enabling fast prototyping of real-time applications on NoC-based MPSoC on FPGA HeartBeat模型:一种平台抽象,可以在FPGA上基于noc的MPSoC上快速构建实时应用的原型
Francesco Robino, Johnny Öberg
{"title":"The HeartBeat model: A platform abstraction enabling fast prototyping of real-time applications on NoC-based MPSoC on FPGA","authors":"Francesco Robino, Johnny Öberg","doi":"10.1109/ReCoSoC.2013.6581536","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2013.6581536","url":null,"abstract":"Future embedded systems will make use of many hundred, configurable or re-configurable, processing elements communicating through a network on chip (NoC), but there is lack of rapid automated design flows bridging the abstraction gap between the models of such systems and their implementation. Designing and programming NoC-based MPSoCs is a complex and error prone activity. However, capturing the design specification at a higher-level of abstraction using models based on models of computation (MoCs) offers a promising way of reducing design flaws at an early stage in the design flow. In this paper, we present the HeartBeat model, a concept for implementing applications based on the synchronous model of computation onto a NoC-based MPSoC platform on FPGA. Furthermore, we show that a platform complying to the constraints imposed by the HeartBeat model has real-time properties. The presented design flow significantly reduces the design time of a real-time embedded system implemented on a NoCbased MPSoC platform, enabling rapid design space exploration through fast prototyping of the solution.","PeriodicalId":354964,"journal":{"name":"2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129647807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Energy-aware dynamic reconfiguration of communication-centric applications for reliable MPSoCs 面向可靠mpsoc的以通信为中心的应用的能量感知动态重构
Anup Das, Ashutosh Kumar Singh, Akash Kumar
{"title":"Energy-aware dynamic reconfiguration of communication-centric applications for reliable MPSoCs","authors":"Anup Das, Ashutosh Kumar Singh, Akash Kumar","doi":"10.1109/ReCoSoC.2013.6581540","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2013.6581540","url":null,"abstract":"To accommodate the ever increasing demands of applications and for the ease of scalability, multiprocessor systems-on-chip (MPSoCs) are becoming a popular design choice in current and future technologies with streaming multimedia and other communication-centric applications constituting a large fraction of the application space. Mapping and scheduling of these applications on an MPSoC to minimize energy consumption while guaranteeing to satisfy the performance requirement is an NP-hard problem. This is coupled with the run-time variability associated with MPSoC resource availability due to the occurrence of faults. The existing studies on fault-tolerance and energy minimization are either based on static (offline) analysis which fails to capture application dynamism or do not consider throughput degradation. This paper proposes an execution trace-based run-time technique to reconfigure application mapping to minimize communication energy of an application, simultaneously dealing with the occurrence of transient, intermittent and permanent faults. Experiments conducted with synthetic and real-life applications modeled using Synchronous Data Flow Graphs (SDFGs) demonstrate that the proposed technique achieves significant improvement with respect to the state-of-the-art approaches in terms of throughput and storage overhead with less than 10% energy overhead.","PeriodicalId":354964,"journal":{"name":"2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129047843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
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