2015 IEEE Non-Volatile Memory System and Applications Symposium (NVMSA)最新文献

MobiLock: an energy-aware encryption mechanism for NVRAM-based mobile devices MobiLock:用于基于nvram的移动设备的能量感知加密机制

2015 IEEE Non-Volatile Memory System and Applications Symposium (NVMSA) Pub Date : 2015-10-29 DOI: 10.1109/NVMSA.2015.7304368

Xianlu Luo, Duo Liu, Liang Liang, Yang Li, Kan Zhong, Linbo Long

{"title":"MobiLock: an energy-aware encryption mechanism for NVRAM-based mobile devices","authors":"Xianlu Luo, Duo Liu, Liang Liang, Yang Li, Kan Zhong, Linbo Long","doi":"10.1109/NVMSA.2015.7304368","DOIUrl":"https://doi.org/10.1109/NVMSA.2015.7304368","url":null,"abstract":"Emerging non-volatile memory (NVRAM) has been considered as the most promising candidate of DRAM for future main memory design in mobile devices. NVRAM-based main memory exhibits attractive features, such as byte-addressability, low standby power, high density and near DRAM performance. However, the nature of non-volatility makes NVRAM vulnerable to be attacked by malicious programs. Though several data encryption techniques have been proposed to solve this problem, they do not consider the limited resources in mobile devices. To address this issue, in this paper, we propose an energyaware encryption mechanism, named MobiLock, to effectively enhance the security of NVRAM-based main memory in mobile devices. The basic idea is to enhance the encryption and decryption performance by utilizing cache and concurrency mechanisms, respectively. To achieve this, we first develop a cache mechanism to cache the encrypted intermediate data (i.e., PAD) whose plaintexts are updated frequently, for accelerating decryption and reducing reamputation of PAD. We then propose a concurrency mechanism to read the ciphertext in NVRAM and calculate the PAD simultaneously, to reduce the decryption latency. The evaluation results show that our technique can effectively reduce encryption energy consumption and decryption latency, respectively.","PeriodicalId":353528,"journal":{"name":"2015 IEEE Non-Volatile Memory System and Applications Symposium (NVMSA)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115193678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Allocation and scheduling of real-time tasks with volatile/non-volatile hybrid memory systems 易失性/非易失性混合存储系统的实时任务分配和调度

2015 IEEE Non-Volatile Memory System and Applications Symposium (NVMSA) Pub Date : 2015-10-29 DOI: 10.1109/NVMSA.2015.7304364

Yuhan Lin, Nan Guan, Qingxu Deng

引用次数: 6

Mixer: software enabled wear leveling for morphable PCM in embedded systems 混合器:嵌入式系统中可变形PCM的软件启用磨损平衡

2015 IEEE Non-Volatile Memory System and Applications Symposium (NVMSA) Pub Date : 2015-10-29 DOI: 10.1109/NVMSA.2015.7304370

Linbo Long, Duo Liu, Liang Liang, Kan Zhong, Xiao Zhu, E. Sha

{"title":"Mixer: software enabled wear leveling for morphable PCM in embedded systems","authors":"Linbo Long, Duo Liu, Liang Liang, Kan Zhong, Xiao Zhu, E. Sha","doi":"10.1109/NVMSA.2015.7304370","DOIUrl":"https://doi.org/10.1109/NVMSA.2015.7304370","url":null,"abstract":"Phase change memory (PCM) is considered as a promising alternative of DRAM-based main memory in embedded systems. A PCM cell can be dynamically programmed to be in either multiple-level cell (MLC) mode or single-level cell (SLC) mode. With this morphable feature, we can utilize the high-density of MLC and low-latency of SLC, to satisfy various memory requirements of specific applications in embedded systems. However, compared to its SLC counterpart, the lifetime of MLC is limited. In particular, a program in embedded systems usually exhibits an extremely unbalanced write pattern, which may accelerate the wear-out of MLC cells in morphable PCM. To address this issue, this paper proposes a simple and effective wear-leveling technique, named Mixer, to enhance the lifetime of morphable PCM considering the program specific features. We first build an Integer Linear Programming (ILP) formulation to produce optimal SLC/MLC partition and data allocation, to achieve a balanced write distribution in morphable PCM with low memory access cost. The basic idea is to allocate fast SLC and MLC cells for write intensive variables and other ordinary variables, respectively. We then propose a polynomial time algorithm to achieve near-optimal results. The evaluation results show that the proposed technique can effectively extend the lifetime of morphable PCM in embedded systems compared with previous work.","PeriodicalId":353528,"journal":{"name":"2015 IEEE Non-Volatile Memory System and Applications Symposium (NVMSA)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132577252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

HMMSim: a simulator for hardware-software co-design of hybrid main memory HMMSim:用于混合主存硬件软件协同设计的仿真器

2015 IEEE Non-Volatile Memory System and Applications Symposium (NVMSA) Pub Date : 2015-10-29 DOI: 10.1109/NVMSA.2015.7304374

S. Bock, B. Childers, R. Melhem, D. Mossé

{"title":"HMMSim: a simulator for hardware-software co-design of hybrid main memory","authors":"S. Bock, B. Childers, R. Melhem, D. Mossé","doi":"10.1109/NVMSA.2015.7304374","DOIUrl":"https://doi.org/10.1109/NVMSA.2015.7304374","url":null,"abstract":"Due to scalability and energy consumption, the use of DRAM as the only main memory technology in modern computers is becoming increasingly less appealing. Researchers have proposed combining DRAM and non-volatile memory (NVM) in main memory to increase capacity and reduce energy consumption. Due to its architectural simplicity, software-managed hybrid memory is a promising way to incorporate NVM. However, there are significant performance issues caused by increased memory traffic due to data migration and a lack of effective migration policies. These issues can be addressed by carefully co-designing hardware-software mechanisms and migration policies. To aid in the development of new mechanisms and policies to incorporate NVM in main memory, we present HMMSim, a trace-driven simulator that allows for fast and flexible exploration of the hardware-software co-design space of hybrid main memory. HMMSim has a simple interface to connect memory hierarchy components that can be configured to simulate several memory architectures, including DRAM only, NVM only, DRAM hardware cache, and software-managed hybrid memory. We present two case studies that use HMMSim, and show that HMMSim is fast, flexible and scalable.","PeriodicalId":353528,"journal":{"name":"2015 IEEE Non-Volatile Memory System and Applications Symposium (NVMSA)","volume":"99 1-4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125986474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Leveraging nonvolatility for architecture design with emerging NVM 利用新兴NVM的架构设计的非易变性

2015 IEEE Non-Volatile Memory System and Applications Symposium (NVMSA) Pub Date : 2015-10-29 DOI: 10.1109/NVMSA.2015.7304356

Shuangchen Li, Ping Chi, Jishen Zhao, K. Cheng, Yuan Xie

引用次数: 10

Logical data packing for multi-chip flash-memory storage systems 多芯片闪存存储系统的逻辑数据封装

2015 IEEE Non-Volatile Memory System and Applications Symposium (NVMSA) Pub Date : 2015-10-29 DOI: 10.1109/NVMSA.2015.7304366

Ming-Chang Yang, Yuan-Hao Chang, Yu-Cheng Chang, Po-Chun Huang

引用次数: 1

Read disturbance issue for nanoscale STT-MRAM 纳米级STT-MRAM的读取干扰问题

2015 IEEE Non-Volatile Memory System and Applications Symposium (NVMSA) Pub Date : 2015-10-29 DOI: 10.1109/NVMSA.2015.7304372

Yi Ran, W. Kang, Youguang Zhang, Jacques-Olivier Klein, Weisheng Zhao

{"title":"Read disturbance issue for nanoscale STT-MRAM","authors":"Yi Ran, W. Kang, Youguang Zhang, Jacques-Olivier Klein, Weisheng Zhao","doi":"10.1109/NVMSA.2015.7304372","DOIUrl":"https://doi.org/10.1109/NVMSA.2015.7304372","url":null,"abstract":"Spin transfer torque magnetic random access memory (STT-MRAM) has been widely considered as one of the most promising candidates for the next-generation nonvolatile memory technologies, thanks to its attractive features, including high density, high speed, low power and high endurance etc. However, our investigation demonstrates that read disturbance may become a big reliability issue of STT-MRAM, since read and write currents share the same path. As technology scales down to nanoscale nodes, this read disturbance issue becomes more serious and may turn into be a critical reliability barrier for STT-MRAM commercialization, because the difference between the read and write currents decreases. In this paper, we propose a circuit to detect the read disturbance by exploiting its typical features, i.e., (a) the resistance (read current) of the memory cell will have a sudden change if read disturbance occurs; (b) only one-direction of read disturbance can occur during normal read operations. Based on the detection results, the correct data can be restored back into the memory cells after read disturbance or system-level algorithms can be employed to correct the read disturbance fault.","PeriodicalId":353528,"journal":{"name":"2015 IEEE Non-Volatile Memory System and Applications Symposium (NVMSA)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132563588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Data-centric garbage collection for NAND flash devices NAND闪存设备的数据中心垃圾收集

2015 IEEE Non-Volatile Memory System and Applications Symposium (NVMSA) Pub Date : 2015-10-29 DOI: 10.1109/NVMSA.2015.7304360

Chundong Wang, Q. Wei, Mingdi Xue, Jun Yang, Cheng Chen

引用次数: 4

Stream query processing on emerging memory architectures 新兴内存架构上的流查询处理

2015 IEEE Non-Volatile Memory System and Applications Symposium (NVMSA) Pub Date : 2015-10-29 DOI: 10.1109/NVMSA.2015.7304367

Chelsea Mafrica, John Johnson, S. Bock, Thao N. Pham, B. Childers, Panos K. Chrysanthis, Alexandros Labrinidis

引用次数: 3

A software-defined fusion storage system for PCM and NAND flash 一种用于PCM和NAND闪存的软件定义融合存储系统

2015 IEEE Non-Volatile Memory System and Applications Symposium (NVMSA) Pub Date : 2015-10-29 DOI: 10.1109/NVMSA.2015.7304361

Zheng Li, Shuangwu Zhang, Jingning Liu, Wei Tong, Yu Hua, D. Feng, C. Yu

{"title":"A software-defined fusion storage system for PCM and NAND flash","authors":"Zheng Li, Shuangwu Zhang, Jingning Liu, Wei Tong, Yu Hua, D. Feng, C. Yu","doi":"10.1109/NVMSA.2015.7304361","DOIUrl":"https://doi.org/10.1109/NVMSA.2015.7304361","url":null,"abstract":"In SSD-based storage systems, persistent data are stored in the NAND Flash and however manipulated in DRAM, causing the decoupled inefficiency. The data being closer to the processors are much easier to be lost due to the volatile property of DRAM, leading to serious data reliability problems. In the meantime, existing SSD technology exploits the properties of NAND Flash and leverages NAND Flash + controller + FTL architecture to improve system's performance. In this black-box-modeled structure, the data semantic information is hard to be transferred by conventional interface. Hence the SSD firmware fails to make full use of the performance potential of SSD in terms of the semantic information of data. Moreover, the host can't obtain physical characteristics and statistical information about SSD, failing to be used by the file system or I/O scheduling algorithm designed for the disks. In order to address these problems, we propose a software defined fusion storage system for PCM and NAND Flash. PCM can be defined as the same level storage or as a buffer of NAND Flash to reduce the WA (Write Amplification) of Flash and improve reliability. In this system, we expose the channels, erases counts and data distribution of PCM/NAND Flash to the host, design FTL algorithm close to file system to obtain more semantic information of data accessing, and manage the storage device as a non-transparent structure. To achieve these design goals, we implement a Host Fusion Storage Layer (HFSL) that supports flexible I/O schedule algorithm and address mapping of variable allocation size in the persistent superior performance of SSD. Extensive experimental results demonstrate the efficiency of the proposed schemes.","PeriodicalId":353528,"journal":{"name":"2015 IEEE Non-Volatile Memory System and Applications Symposium (NVMSA)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114263503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9