Logical data packing for multi-chip flash-memory storage systems

Abstract

The multi-chip architecture is a popular development trend to let flash storage devices support both high access parallelism and large storage capacity. Nevertheless, the adoption of multi-chip architecture might contradict the design goal of some existing designs. For example, parallel accesses/writes to multiple chips could hinder the outcome of hot/cold data separation. Different from the existing hot/cold separation designs that only separate frequently accessed data from infrequently accessed ones, this work puts forward the concept of logical data packing to improve the performance of multi-chipped flash storage devices. In particular, by capturing both temporal and spatial localities of data accesses, the proposed logical data packing design can proactively store data in proper physical space so that the data migration overheads during garbage collection can be minimized. The proposed scheme was evaluated based on representative realistic workloads. The results show that the proposed design can improve the device performance by 5%-61% and extend the device lifetime by 6.5%-15.5%.