{"title":"A self-driven active reset converter for low-voltage high-current applications","authors":"P. Kumar","doi":"10.1109/APEC.2000.822580","DOIUrl":"https://doi.org/10.1109/APEC.2000.822580","url":null,"abstract":"An improved self-driven active reset forward converter for low-voltage high-current applications is presented. The converter is derived from the operation of an active clamp forward. The suitability of the proposed converter for high frequency operation is illustrated. The advantages of the proposed converter in terms of simple drive requirements are explained. The converter is shown to exhibit reduced output ripple contents even with reduced output filter components. Experimental results are presented substantiating the operational features of the converter.","PeriodicalId":347959,"journal":{"name":"APEC 2000. Fifteenth Annual IEEE Applied Power Electronics Conference and Exposition (Cat. No.00CH37058)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114985061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A novel partial series resonant DC/DC converter with zero-voltage/zero-current switching","authors":"Eui-Sung Kim, Dong-Yun Lee, D. Hyun","doi":"10.1109/APEC.2000.826089","DOIUrl":"https://doi.org/10.1109/APEC.2000.826089","url":null,"abstract":"This paper presents a new soft-switching partial series resonant DC/DC converter (PSRC) with zero-voltage/zero-current switching (ZV/ZCS), suitable for application in the high power and high frequency switching. The proposed converter has not only advantages of the conventional PSRC but also ZV/ZCS of the main switch for the entire load ranges by adding the auxiliary circuit, and zero-voltage-switching (ZVS) turn-on of the auxiliary switch. The auxiliary network consists of the auxiliary switches, two auxiliary capacitors, an auxiliary inductor, two auxiliary diodes and saturable inductor and added to ZV/ZCS of the main switch. The operation principles of the new converter are explained in detail and the several interesting simulated and experimental results verify the validity of the proposed circuit.","PeriodicalId":347959,"journal":{"name":"APEC 2000. Fifteenth Annual IEEE Applied Power Electronics Conference and Exposition (Cat. No.00CH37058)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122433397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Processor power subsystem architectures","authors":"R. Kollman, D. Chamberlin","doi":"10.1109/APEC.2000.822837","DOIUrl":"https://doi.org/10.1109/APEC.2000.822837","url":null,"abstract":"This trade study compares the cost, weight, volume and reliability of a power subsystem for an avionic processor. It considers a range of options from a centralized power subsystem to a distributed subsystem with an intermediate bus. The centralized approach was found unsuitable for the lower voltage logic devices that will come to the market over the next few years, a distributed approach will be required. An intermediate voltage bus is preferred over prime power distribution due to safety, high voltage insulation and failure modes effects. Choices of the intermediate bus voltage favor lower voltages which allow the use of buck regulators rather than a transformer coupled approach. An intermediate voltage system using buck regulators provides: 50% cost savings; 20% weight reduction; 25 volume reduction; and 75% reliability improvement when compared to a higher (50 V) distribution voltage.","PeriodicalId":347959,"journal":{"name":"APEC 2000. Fifteenth Annual IEEE Applied Power Electronics Conference and Exposition (Cat. No.00CH37058)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125004680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A novel single-phase active-clamped ZVT-PWM PFC converter","authors":"D.M. Xu, J.M. Zhang, X. Wu, Y. Ren, Z. Qian","doi":"10.1109/APEC.2000.826143","DOIUrl":"https://doi.org/10.1109/APEC.2000.826143","url":null,"abstract":"A novel single-phase active-clamped power factor correction converter is proposed. Based on the constant frequency and the resonant active-clamped techniques. This circuit realizes ZVT of the main switch and ZCS of the auxiliary switch. In the full range of loads, it can be operated at constant frequency soft-switching mode. Finally, the PSPICE simulation and experiment results of a 3 kW 100 kHz PFC converter are presented, whose efficiency is as high as 97%.","PeriodicalId":347959,"journal":{"name":"APEC 2000. Fifteenth Annual IEEE Applied Power Electronics Conference and Exposition (Cat. No.00CH37058)","volume":"1 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123622509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A topology survey of single-stage power factor corrector with a boost type input-current-shaper","authors":"Chunming Qiao, Keyue Smedley","doi":"10.1109/APEC.2000.826144","DOIUrl":"https://doi.org/10.1109/APEC.2000.826144","url":null,"abstract":"A topological review of the single stage power factor corrected (PFC) rectifiers is presented in this paper. Most of reported single-stage PFC rectifiers cascade a boost type converter with a forward or a flyback DC-DC converter so that input current shaping, isolation, and fast output voltage regulation are performed in one single stage. The cost and performance of a single-stage PFC converters depend greatly on how its input current shaper (ICS) and the DC-DC converter are integrated together. For the cascade connected single-stage PFC rectifiers, the energy storage capacitor is found in either series or parallel path of energy flow. The second group appears to represent the main stream. Therefore, the focus of this paper is on this group. It is found that many of these topologies can be implemented by combining a 2-terminal or 3-terminal boost ICS cell with DC-DC converter along with an energy storage capacitor in between. A general rule is observed that translates a 3-terminal ICS cell to a 2-terminal ICS cell using an additional winding from the transformer and vice versa. According to the translation rule, many of reported single-stage PFC topologies can be viewed as electrically equivalent to one another. Several new PFC converters were derived from some existing topologies using the translation rule.","PeriodicalId":347959,"journal":{"name":"APEC 2000. Fifteenth Annual IEEE Applied Power Electronics Conference and Exposition (Cat. No.00CH37058)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129970073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A critical-conduction-mode single-stage power-factor-correction electronic ballast","authors":"F. Tao, F. Lee","doi":"10.1109/APEC.2000.826165","DOIUrl":"https://doi.org/10.1109/APEC.2000.826165","url":null,"abstract":"A critical-conduction-mode single-stage power-factor-correction (PFC) electronic ballast is presented in this paper. The proposed ballast combines the power-factor-correction stage with a conventional half bridge DC/AC inverter into a single-stage to reduce the cost. The power factor correction stage is a boost-like converter operating in critical conduction mode so that a high power factor is achieved naturally. By exploiting voltage divider, the ratio of line peak voltage to DC-bus voltage can be chosen as a large value of near one, yet a good power factor can be achieved. Theoretical analysis and experimental results for two 45-watt fluorescent lamps are presented.","PeriodicalId":347959,"journal":{"name":"APEC 2000. Fifteenth Annual IEEE Applied Power Electronics Conference and Exposition (Cat. No.00CH37058)","volume":"228 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120889642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A new concept for minimizing high-frequency common-mode EMI of three-phase PWM rectifier systems keeping high utilization of the output voltage","authors":"J. Kolar, U. Drofenik, J. Minibock, H. Ertl","doi":"10.1109/APEC.2000.826153","DOIUrl":"https://doi.org/10.1109/APEC.2000.826153","url":null,"abstract":"Three-phase PWM rectifier systems in principle show a common-mode voltage with switching frequency between the mains neutral point and the center point of the output voltage. Without any counter-measures this leads to a high common-mode noise emission of the system and possibly to disturbances of the control unit of the converter being fed by the rectifier. In this paper a detailed discussion of the formation of the common-mode voltage for the VIENNA Rectifier I is given and a modified circuit topology which significantly reduces the switching frequency component of the common-mode voltage is given. The proposed circuit modification is applicable also to other three-phase PWM rectifier topologies. The filtering concept is analyzed by digital simulation and guidelines for the dimensioning of the filter components are given. The reduction of the common-mode noise is verified by EMI measurements taken from a 10 kW laboratory unit of a VIENNA Rectifier I. Finally, the advantages and drawbacks of the proposed filtering concept are compiled in the form of an overview.","PeriodicalId":347959,"journal":{"name":"APEC 2000. Fifteenth Annual IEEE Applied Power Electronics Conference and Exposition (Cat. No.00CH37058)","volume":"16 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120905336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Optimally selecting packaging technologies and circuit partitions based on cost and performance","authors":"J. Jacobsen, D. Hopkins","doi":"10.1109/APEC.2000.826079","DOIUrl":"https://doi.org/10.1109/APEC.2000.826079","url":null,"abstract":"Most power electronics circuits are packaged using two or more power electronics packaging technologies. To optimally select and use several technologies that meet performance requirements at minimum cost requires a strategic partitioning of the circuit. Presented is a structured technique for optimally selecting technologies based on a relative cost diagram. Other factors, such as performance, product volume and modularity are included.","PeriodicalId":347959,"journal":{"name":"APEC 2000. Fifteenth Annual IEEE Applied Power Electronics Conference and Exposition (Cat. No.00CH37058)","volume":"360 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116558829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Comparison of the state-of-the-art high power IGBTs, GCTs and ETOs","authors":"K. Motto, Y. Li, A. Huang","doi":"10.1109/APEC.2000.822829","DOIUrl":"https://doi.org/10.1109/APEC.2000.822829","url":null,"abstract":"In this paper, a comparison of three semiconductor devices suitable for high power applications is presented. All devices feature high switching speed and snubberless turn-off capability. The devices compared include one high voltage insulated gate bipolar transistor (HVIGBT) and two types of hard-driven GTO thyristor-the gate commutated turn-off (GCT) thyristor and the emitter turn-off (ETO) Thyristor. The conduction and switching characteristics are compared, and an assessment is presented of the impact on high-power converter circuits for these devices. Test results are shown.","PeriodicalId":347959,"journal":{"name":"APEC 2000. Fifteenth Annual IEEE Applied Power Electronics Conference and Exposition (Cat. No.00CH37058)","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126163488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Accurate rotor position detection and sensorless control of SRM for super-high speed operation","authors":"Longya Xu, Chuanyang Wang","doi":"10.1109/APEC.2000.826129","DOIUrl":"https://doi.org/10.1109/APEC.2000.826129","url":null,"abstract":"Based on the general nonlinear magnetizing model (GNMM) from the authors' previous research work, an improved method of detecting rotor position for sensorless control of SRMs in super-high speed operation has been developed. With minimum input data, the approximated GNMM is obtained and the rotor speed estimated. Then the rotor position is detected by the motion equation. To remove error, the proposed scheme updates the reference for rotor position detection at critical points using the flux observation and the GNMM is adaptively tuned. The improved rotor position detection method has been implemented by fully exploring the computation power of the modern DSP. Laboratory testing on different types of SRMs with sensorless control up to 20,000 RPM is accomplished.","PeriodicalId":347959,"journal":{"name":"APEC 2000. Fifteenth Annual IEEE Applied Power Electronics Conference and Exposition (Cat. No.00CH37058)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126065207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}