RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics最新文献_第3页

An overview of innovation ecosystem in Malaysia 马来西亚创新生态系统概述

RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics Pub Date : 2013-09-01 DOI: 10.1109/RSM.2013.6706568

Masuri BinOthman

{"title":"An overview of innovation ecosystem in Malaysia","authors":"Masuri BinOthman","doi":"10.1109/RSM.2013.6706568","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706568","url":null,"abstract":"Malaysia aspires to become high income nation by 2020. The Government Transformation Program (GTP) has set by 2020, the GNI percapita will be RM48,000 and the creation of high-income jobs of 3.3 Millions. In order to achieve the desired outcome, the government has identified 12 NKEA areas with 131 entry point projects to be carried out. One of the 12 NKEAs which is Electrical and Electronics is expected to create GNI of RM90B and the creation of 157,000 jobs. The areas identified in the E&E are LED, Solar, industrial electronics and home appliances, Semiconductor as well as nanotechnology that will include the creation of whole value chain industry. Additionally the National Science and Research Council (NSRC) has identified 9 sectors that Malaysia must pursue for it to become a competitive nation in the future. Thus for Malaysia to succeed in the future, its innovation ecosystem must be strengthen and improved; thus The Quadruple Helix framework; ie the collaboration between IHLs and Industry supported by government policies and financial supports must be promoted. This presentation will address the issues of the innovation ecosystem and the quadruple helix. The roles of industry; ie particularly in the technology deployment in the GTP/ETP initiatives as well as various corridors across the country will be linked to the IHLs through the setting up of the COEs in the universities. Various grants schemes to support the R&D&C will be highlighted and some of the issues in the technology commercialisation will be presented. Some proposals in the creation of High Impact Research programs will be proposed that in line with the GTP/ETP which could be funded by various government funding agencies.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"154 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127340582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A simulation study of thickness effect in performance of double lateral gate junctionless transistors 厚度对双侧栅无结晶体管性能影响的仿真研究

RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics Pub Date : 2013-09-01 DOI: 10.1109/RSM.2013.6706480

F. Larki, A. Dehzangi, M. Hamidon, S. Ali, A. Jalar, Shabiul Islam

引用次数: 1

Fabrication and characterization of polysilicon nanogap device for DNA hybridization detection DNA杂交检测用多晶硅纳米隙器件的制备与表征

RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics Pub Date : 2013-09-01 DOI: 10.1109/RSM.2013.6706567

U. Hashim

{"title":"Fabrication and characterization of polysilicon nanogap device for DNA hybridization detection","authors":"U. Hashim","doi":"10.1109/RSM.2013.6706567","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706567","url":null,"abstract":"Summary form only given. Fabrication and electrical characterization of 5-nm polysilicon gaps and their properties are discussed with their application in electrochemical sensors and biomolecule detection. To understand the relationship between the biosensor and nanotechnology we have carried out the fabrication and characterization of nanogap structures for DNA detection. In this paper, 2 mask designs are used. The first mask is for defining the lateral nanogap and the second mask is for the pad electrode pattern. Lateral nanogaps are formed using polysilicon and Au as the contact pad electrode. Conventional photolithography technique is used to fabricate the nanoogap structure. The electrical measurements are carried out using Dielectric Analyzer. The capacitance across the nanoogap was noted to change with probing and when target DNA solution is dropped between the gaps. The measured values of capacitance for the probe and target DNA solution are presented as a function of the frequency, where, the capacitance values were increased after immobilization of the target DNA and double increased after hybridization of the target DNA.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124977791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Annealing effects on structural and electrical properties of micro heater conductor element 退火对微加热导体元件结构和电性能的影响

RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics Pub Date : 2013-09-01 DOI: 10.1109/RSM.2013.6706477

N. Hamid, B. Majlis, J. Yunas, A. Dehzangi

{"title":"Annealing effects on structural and electrical properties of micro heater conductor element","authors":"N. Hamid, B. Majlis, J. Yunas, A. Dehzangi","doi":"10.1109/RSM.2013.6706477","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706477","url":null,"abstract":"This paper presents an analysis and investigation of the effect thermal anealing treatment on structural and electrical properties of micro heater conductor. Conventional micro fabrication process has given a higher resistance impact on the heater conductor properties. Higher conductor resistance obtains higher source for micro heater to be operated. Since the micro heater is used for micron-sized devices, only small amount of source is consumed for the micro component. Therefore annealing process is necessary to reduce the resistance of metal conductor heater. In this work, the thermal annealing treatment process was carried out in nitrogen atmosphere at temperature of 450°C for 30 minutes. Structural properties were studied using Scanning Electron Microscopy (SEM) and Atomic Force Microscopy (AFM) while an electrical property was investigated using heater characterization measurement and testing. The analysis shows that thermal annealing treatment improved the electrical properties of the heater conductor element and provided some changes in samples, such as the grain size increment or the decrease of the strain.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"214 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126993549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Effect of RF sputtered arc-TiO2 and sol-gel c-TiO2 compact layers on the performance of dye-sensitized solar cell RF溅射arc-TiO2和溶胶-凝胶c-TiO2致密层对染料敏化太阳能电池性能的影响

RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics Pub Date : 2013-09-01 DOI: 10.1109/RSM.2013.6706498

M. H. Abdullah, I. Saurdi, M. Rusop

引用次数: 3

Photoanode of nanostructured TiO2 prepared by ultrasonic irradiation assisted of sol-gel with P-25 for dye-sensitized Solar Cells P-25溶胶-凝胶辅助超声辐照法制备染料敏化太阳能电池用纳米TiO2光阳极

RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics Pub Date : 2013-09-01 DOI: 10.1109/RSM.2013.6706524

I. Saurdi, M. H. Mamat, M. Musa, M. Amalina, M. H. Abdullah, M. Rusop

{"title":"Photoanode of nanostructured TiO2 prepared by ultrasonic irradiation assisted of sol-gel with P-25 for dye-sensitized Solar Cells","authors":"I. Saurdi, M. H. Mamat, M. Musa, M. Amalina, M. H. Abdullah, M. Rusop","doi":"10.1109/RSM.2013.6706524","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706524","url":null,"abstract":"In this work, TiO2 photoanode have been prepared by mixing the commercial titania powder P-25 with a titanium sol gel. In order to improve the mixing condition the paste was gone through the ultrasonic treatment. After that, the doctor blade technique was used to deposit TiO2 paste on ITO-coated glass substrate. There were two monolayer photoanodes with ultrasonic and without ultrasonic TiO2 pastes of about the same thickness have been prepared and their effects on the overall cell performances of the DSSC were compared. From the solar simulator measurement the solar energy conversion efficiency (η) of 2.6642% under AM 1.5 was obtained with the ultrasonic photoanode DSSC which correspond to the short-circuit photocurrent density (Jsc) and open-circuit voltage (Voc) of 7.2552 mA/cm2 and 0.5168 V, respectively, while 1.3127% conversion efficiency (η) obtained from without ultrasonic TiO2 photoanode. The TiO2 photoanode with ultrasonic were efficiently in the fabrication process of dye-sensitized solar cells (DSSCs), where the improvement which was almost double from unsonicated film for the overall energy conversion efficiency (η) that achieved for the sonicated TiO2 photoanode with the present of PEG.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127750273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Design and simulation of 20MHz oscillator using CMOS-MEMS beam resonators 基于CMOS-MEMS波束谐振器的20MHz振荡器设计与仿真

RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics Pub Date : 2013-09-01 DOI: 10.1109/RSM.2013.6706469

Ahmad Anwar Zainuddin, J. Karim, A. Nordin, M. S. Pandian, S. Khan

{"title":"Design and simulation of 20MHz oscillator using CMOS-MEMS beam resonators","authors":"Ahmad Anwar Zainuddin, J. Karim, A. Nordin, M. S. Pandian, S. Khan","doi":"10.1109/RSM.2013.6706469","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706469","url":null,"abstract":"We present the design and analysis result of a low power, low noise, 20 MHz CMOS-MEMS oscillators. To perform oscillator circuit simulations, the CMOS-MEMS resonator (Clamped-Clamped beam) was modeled using its RLC equivalent circuits. For a MEMS resonator to be able to function as an oscillator it needs to be coupled with supporting amplifier circuits. The MEMS beam resonator has 73dB insertion loss which translates to motional resistance of Rx=3MΩ, capacitance, Cx=4.58aF and inductance, Lx=14.5H respectively. The amplifier design is based on the requirement for oscillation, which is, the loop gain of one and the zero phase shifts. For this work, the pierce circuit topology was chosen due to its simplicity and high frequency stability. Both the amplifier and beam resonators were designed using Silterra's CMOS technology. The design of the amplifier comprises of 6 transistors, which are integrated with the MEMS beam resonator to form an oscillator. The proposed CMOS-MEMS oscillators is capable of generating 20 MHz clocks. The beam resonators require approximately 40VDC and 400mV, VAC to vibrate. The actuation was simulated and measured using Finite modeling software, FEM and Cadence to obtain the desired design parameters. The design of 20MHz oscillator produces output power -1.45dBm by using 1.8V power supply.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128140820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Physical properties of tin oxide thin films deposited using magnetron sputtering technique 磁控溅射沉积氧化锡薄膜的物理性质

RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics Pub Date : 2013-09-01 DOI: 10.1109/RSM.2013.6706549

Huey Sia Lim, N. Nayan, M. Z. Sahdan, S. Dahlan, M. K. Suaidi, F. M. Johar, G. Kiani

引用次数: 0

Design of CMOS-MEMS based thermoelectric generator 基于CMOS-MEMS的热电发电机设计

RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics Pub Date : 2013-09-01 DOI: 10.1109/RSM.2013.6706460

Z. H. A. Rahman, M. H. M. Md Khir, Z. A. Burhanudin, A. Rahman, W. A. W. Jamil

{"title":"Design of CMOS-MEMS based thermoelectric generator","authors":"Z. H. A. Rahman, M. H. M. Md Khir, Z. A. Burhanudin, A. Rahman, W. A. W. Jamil","doi":"10.1109/RSM.2013.6706460","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706460","url":null,"abstract":"This paper presents the design of micro-scale thermoelectric generator (TEG) using CMOS-MEMS technology. Electrical energy is obtained by means of thermal energy harvesting technique. Thermal energy harvesting has become a promising solution to power up low power system such as wireless sensor networks (WSNs) and portable devices. Thermal energy or heat which is widely available in natural and also human made environments can be converted into electrical power using Seebeck effect. The proposed TEG is compatible with standard CMOS technology which consists of p-doped and n-doped polysilicon thermocouples arranged electrically in series and thermally in parallel. In order to increase the temperature difference between the hot and cold parts, a layer of heat sink with low thermal conductivity material is insulated at the cold part area. Trenches are included in-between each thermocouple to disperse heat efficiently to ambient air. Post-CMOS process is included to illustrate proper procedures for a successful device release. Simulation results show that with temperature difference of 10 K, output voltage and power attained is 301 mV and 45 μW, respectively.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115446943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Threshold voltage optimization in a 22nm High-k/Salicide PMOS device 22nm高k/Salicide PMOS器件的阈值电压优化

RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics Pub Date : 2013-09-01 DOI: 10.1109/RSM.2013.6706489

A. Maheran, P. Menon, I. Ahmad, Z. Yusoff

{"title":"Threshold voltage optimization in a 22nm High-k/Salicide PMOS device","authors":"A. Maheran, P. Menon, I. Ahmad, Z. Yusoff","doi":"10.1109/RSM.2013.6706489","DOIUrl":"https://doi.org/10.1109/RSM.2013.6706489","url":null,"abstract":"In this article, we examine the effect of four process parameters and two noise parameters on the threshold voltage (Vth) of a 22nm gate length PMOS device. The gate of the device uses titanium dioxide (TiO2) as the high permittivity material (high-k) layer to replace the traditional silicon dioxide (SiO2) dielectric layer. While the polysilicon (poly-Si) which is also known as self-aligned silicide (SALICIDE) layer, is deposited on top of the high-k dielectric layer and is used to reduce the gate electrode resistance. The virtual fabrication device was designed using the ATHENA and electrical characterization was simulated using ATLAS. These two simulators were combined with the L9 Taguchi's experimental design to aid in the design and optimization of the process parameters for a total of 36 simulation runs. The objective is to minimize the variance in Vth using Taguchi's nominal-the-best signal-to-noise ratio (SNR) analysis. Analysis of the mean (ANOM) was used to determine the best settings for the process parameters while Analysis of variance (ANOVA) was used to reduce the variability of Vth. The results show that the Vth values with the least variance is -0.289 V ± 12.7% which is well within the prediction by the International Technology Roadmap for Semiconductors (ITRS) 2011.","PeriodicalId":346255,"journal":{"name":"RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123036359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5