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2008 IEEE International Conference on Computer Design最新文献

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An improved micro-architecture for function approximation using piecewise quadratic interpolation 基于分段二次插值的函数逼近改进微结构
2008 IEEE International Conference on Computer Design Pub Date : 2008-10-01 DOI: 10.1109/ICCD.2008.4751895
Shai Erez, G. Even
{"title":"An improved micro-architecture for function approximation using piecewise quadratic interpolation","authors":"Shai Erez, G. Even","doi":"10.1109/ICCD.2008.4751895","DOIUrl":"https://doi.org/10.1109/ICCD.2008.4751895","url":null,"abstract":"We present a new micro-architecture for evaluating functions based on piecewise quadratic interpolation. The micro-architecture consists mainly of a look-up table and two multiply-accumulate units. Previous micro-architectures based on piecewise quadratic interpolation have been shown to be efficient for small precision (e.g., single precision) computations. Moreover, they are as fast as piecewise linear interpolation while requiring smaller tables. Our main contribution is in circumventing the need for the additional squaring unit that appears in previous micro-architectures. Based on the proposed micro-architecture, we present a detailed design of single precision reciprocal approximation (1/x). Our design is based on two multiply-accumulate units that contain truncated Booth radix 4 multipliers. The number of partial products in this design is reduced by over 20% compared to previous designs using quadratic interpolation. The latency of this design is roughly the delay of 19 full-adder gates, and it can be easily pipelined into two stages each with a delay of 10 full-adder gates.","PeriodicalId":345501,"journal":{"name":"2008 IEEE International Conference on Computer Design","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121578718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A study of reliability issues in clock distribution networks 时钟分配网络可靠性问题研究
2008 IEEE International Conference on Computer Design Pub Date : 2008-10-01 DOI: 10.1109/ICCD.2008.4751847
Aida Todri-Sanial, M. Marek-Sadowska
{"title":"A study of reliability issues in clock distribution networks","authors":"Aida Todri-Sanial, M. Marek-Sadowska","doi":"10.1109/ICCD.2008.4751847","DOIUrl":"https://doi.org/10.1109/ICCD.2008.4751847","url":null,"abstract":"In this paper, we present a reliability study of clock mesh distribution networks. We analyze the electromigration (EM) phenomena and demonstrate their occurrence in clock mesh networks (CMN). Due to shrinking feature sizes in more advanced technologies, EM is becoming a more prominent reliability issue. Process variation, power supply noise, and clock gating are some of the factors that can increase electromigration in the clock mesh. We identity the potential EM branches by investigating current flows under various conditions. Our study shows that a clock mesh optimized for certain configurations of clock sinks may experience electromigration due to asymmetrical bidirectional currents flowing in some grid segments.","PeriodicalId":345501,"journal":{"name":"2008 IEEE International Conference on Computer Design","volume":"69 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122775510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
ECO-Map: Technology remapping for post-mask ECO using simulated annealing ECO- map:利用模拟退火技术对掩模后ECO进行重新映射
2008 IEEE International Conference on Computer Design Pub Date : 2008-10-01 DOI: 10.1109/ICCD.2008.4751930
Nilesh A. Modi, M. Marek-Sadowska
{"title":"ECO-Map: Technology remapping for post-mask ECO using simulated annealing","authors":"Nilesh A. Modi, M. Marek-Sadowska","doi":"10.1109/ICCD.2008.4751930","DOIUrl":"https://doi.org/10.1109/ICCD.2008.4751930","url":null,"abstract":"With transistor mask costs soaring and the delays associated with full design re-spins escalating, post-mask Engineering Change Orders (ECOs) - design changes after the masks have been prepared - are increasingly carried out by keeping transistor masks intact and revising only the metal masks. In this paper, we propose a novel design flow for achieving technology remapping for post-mask ECOs. In contrast to conventional technology mapping and placement algorithms that have no notion of the quantity for each gate type and the location of placed spare/recycled cells, our flow ECO-Map provides an ideal scalable framework for achieving global optimization in a post-mask ECO scenario. Given the changed logic due to a functional ECO and a limited number of placed spare/recycled cells, ECO-Map finds a resource-feasible Boolean cover and optimally fits the changed logic into the available resources. This ensures minimal perturbation of the existing solution and keeps transistor masks intact, thus reducing non-recurring engineering (NRE) costs. Experiments performed on MCNC benchmarks show the effectiveness of our approach.","PeriodicalId":345501,"journal":{"name":"2008 IEEE International Conference on Computer Design","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124650715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Bridging the gap between nanomagnetic devices and circuits 弥合纳米磁性器件和电路之间的差距
2008 IEEE International Conference on Computer Design Pub Date : 2008-10-01 DOI: 10.1109/ICCD.2008.4751908
M. Niemier, X. Hu, A. Dingler, M. Alam, G. Bernstein, W. Porod
{"title":"Bridging the gap between nanomagnetic devices and circuits","authors":"M. Niemier, X. Hu, A. Dingler, M. Alam, G. Bernstein, W. Porod","doi":"10.1109/ICCD.2008.4751908","DOIUrl":"https://doi.org/10.1109/ICCD.2008.4751908","url":null,"abstract":"This paper looks at designing circuit elements that will be constructed with nanoscale magnets within the Quantum-dot Cellular Automata (QCA) computational paradigm. In magnetic QCA (MQCA) logical operations and dataflow are accomplished by manipulating the polarizations of nanoscale magnets. Wires and gates have already been experimentally demonstrated at room temperature. However, to realize more complex circuits - and eventually systems - more than just wires and gates in isolation are required. For example, gates must be inter-connected, signals must cross, etc. All structures must be controlled by the envisioned drive circuitry. In this paper, structures that will facilitate these circuit-level tasks are presented for the first time.","PeriodicalId":345501,"journal":{"name":"2008 IEEE International Conference on Computer Design","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123336040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Adaptive SRAM memory for low power and high yield 低功耗、高产率的自适应SRAM存储器
2008 IEEE International Conference on Computer Design Pub Date : 2008-10-01 DOI: 10.1109/ICCD.2008.4751858
B. Mohammad, Stephen Bijansky, A. Aziz, J. Abraham
{"title":"Adaptive SRAM memory for low power and high yield","authors":"B. Mohammad, Stephen Bijansky, A. Aziz, J. Abraham","doi":"10.1109/ICCD.2008.4751858","DOIUrl":"https://doi.org/10.1109/ICCD.2008.4751858","url":null,"abstract":"SRAMs typically represent half of the area and more than half of the transistors on a chip today. Variability increases as feature size decreases, and the impact of variability is especially pronounced on SRAMs since they make extensive use of minimum sized devices. Variability leads to a large amount of guard banding in the design phase in order to meet frequency and yield targets. We develop an SRAM architecture that eliminates guard banding. Specifically, our SRAM uses multiple supply voltages that are assigned post-manufacturing. We compensate for variation by powering up manufactured devices that are slower than designed. Specifically, we assign supply voltages to 6T cells on a per-column basis; this gives us sufficiently fine-grained control over devices without excessive area overhead. We show that post-manufacturing voltage assignment results in a 28% reduction in bitline energy compared to a fixed voltage design for the same yield using data from a real-world 45 nm process.","PeriodicalId":345501,"journal":{"name":"2008 IEEE International Conference on Computer Design","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129664696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Modeling and analysis of non-rectangular transistors caused by lithographic distortions 光刻变形引起的非矩形晶体管建模与分析
2008 IEEE International Conference on Computer Design Pub Date : 2008-10-01 DOI: 10.1109/ICCD.2008.4751899
Aswin Sreedhar, S. Kundu
{"title":"Modeling and analysis of non-rectangular transistors caused by lithographic distortions","authors":"Aswin Sreedhar, S. Kundu","doi":"10.1109/ICCD.2008.4751899","DOIUrl":"https://doi.org/10.1109/ICCD.2008.4751899","url":null,"abstract":"Sub-wavelength lithography causes the shape of transistors to differ from idealized rectangles. Several researchers have proposed transistor simulation models to characterize the non-ideal shapes of transistors for various regions of transistor operation. It has been shown that the effective channel length of a non-rectangular gate (NRG) transistor may be different for ON and OFF currents. In this paper we present a composite post-litho non-rectangular transistor model that not only accounts for DC behavior of a transistor, but also accounts for parasitic capacitances across a range of voltages. Parameters of this model can be fitted to real silicon data. The proposed model has been validated by TCAD device simulations. Results show that a composite model that accounts for both DC currents and parasitic capacitances is no more complex than models optimized for DC currents only. Further, the proposed model integrates readily with available SPICE simulators. We have also presented cell library characterization data to illustrate the benefit of using a delay accurate transistor model.","PeriodicalId":345501,"journal":{"name":"2008 IEEE International Conference on Computer Design","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130299475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Pre-Si estimation and compensation of SRAM layout deficiencies to achieve target performance and yield 预si估计和补偿SRAM布局缺陷，以达到目标性能和良率
2008 IEEE International Conference on Computer Design Pub Date : 2008-10-01 DOI: 10.1109/ICCD.2008.4751901
A. Bansal, Rama N. Singh, S. Mukhopadhyay, G. Han, Fook-Luen Heng, C. Chuang
{"title":"Pre-Si estimation and compensation of SRAM layout deficiencies to achieve target performance and yield","authors":"A. Bansal, Rama N. Singh, S. Mukhopadhyay, G. Han, Fook-Luen Heng, C. Chuang","doi":"10.1109/ICCD.2008.4751901","DOIUrl":"https://doi.org/10.1109/ICCD.2008.4751901","url":null,"abstract":"With technology scaling, process constraints and imperfections result in significant variation of post-Si performance and stability of SRAM from designed/target pre-Si parameters. Modification/ re-optimization of SRAM cell and/or tuning of process parameters to meet target performance and stability are limited by area constraints and involve several technology ramp-up cycles. For reducing access failures, if process is not fine tuned, memory access clock cycle period may need to be increased thereby compromising performance. We propose a design methodology to meet the target performance and reduce access failures by tuning the SRAM array peripherals instead of tuning the SRAM cell and process parameters. Proposed design methodology is supported by numerical framework and validated by simulation results on 45 nm PDSOI technology. We further show that our methodology does not impact the READ stability of a cell.","PeriodicalId":345501,"journal":{"name":"2008 IEEE International Conference on Computer Design","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126968215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Improving SAT-based Combinational Equivalence Checking through circuit preprocessing 通过电路预处理改进基于sat的组合等效性检测
2008 IEEE International Conference on Computer Design Pub Date : 2008-10-01 DOI: 10.1109/ICCD.2008.4751838
F. V. Andrade, L. M. Silva, A. O. Fernandes
{"title":"Improving SAT-based Combinational Equivalence Checking through circuit preprocessing","authors":"F. V. Andrade, L. M. Silva, A. O. Fernandes","doi":"10.1109/ICCD.2008.4751838","DOIUrl":"https://doi.org/10.1109/ICCD.2008.4751838","url":null,"abstract":"This paper presents a new implication tool (Vimplic) which can be used to improve SAT-based combinational equivalence checking. This tool quickly builds the implication graph of the miter circuit and traverse through it inferring implications among its nodes assignments. This set of implications and the miter circuit netlist are converted to conjunctive normal form (CNF) and submitted to the SAT solver in order to prove equivalence between the two circuits of the miter. Using Vimplic we have been able to dramatically reduce the overall verification time of several circuits outperforming the state-of-the-art techniques for CEC such as Berkmin561, NiVER, and C-SAT.","PeriodicalId":345501,"journal":{"name":"2008 IEEE International Conference on Computer Design","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122076256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Propositional approximations for bounded model checking of partial circuit designs 部分电路设计有界模型检验的命题逼近
2008 IEEE International Conference on Computer Design Pub Date : 2008-10-01 DOI: 10.1109/ICCD.2008.4751840
B. Becker, Marc Herbstritt, Natalia Kalinnik, Matthew D. T. Lewis, Juri Lichtner, Tobias Nopper, Ralf Wimmer
{"title":"Propositional approximations for bounded model checking of partial circuit designs","authors":"B. Becker, Marc Herbstritt, Natalia Kalinnik, Matthew D. T. Lewis, Juri Lichtner, Tobias Nopper, Ralf Wimmer","doi":"10.1109/ICCD.2008.4751840","DOIUrl":"https://doi.org/10.1109/ICCD.2008.4751840","url":null,"abstract":"Bounded model checking of partial circuit designs enables the detection of errors even when the implementation of the design is not finished. The behavior of the missing parts can be modeled by a conservative extension of propositional logic, called 01X-logic. Then the transitions of the underlying (incomplete) sequential circuit under verification have to be represented adequately. In this work, we investigate the difference between a relation-oriented and a function-oriented approach for this issue. Experimental results on a large set of examples show that the function-oriented representation is most often superior w. r. t. (1) CPU runtime and (2) accuracy regarding the ability to find a counterexample, such that by using the function-oriented approach an increase of accuracy up to 210% and a speed-up of the CPU runtime up to 390% compared to the relation-oriented approach are achieved. But there are also relevant examples, e. g. a VLIW-ALU, for which the relation-oriented approach outperforms the function-oriented one by 300% in terms of CPU-time, showing that both approaches are efficient for different scenarios.","PeriodicalId":345501,"journal":{"name":"2008 IEEE International Conference on Computer Design","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125604969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A macromodel technique for VLSI dynamic simulation by mapping pre-characterized transitions 一种基于映射预表征跃迁的VLSI动态仿真宏模型技术
2008 IEEE International Conference on Computer Design Pub Date : 2008-10-01 DOI: 10.1109/ICCD.2008.4751900
Dimitrios Bountas, G. Stamoulis, N. Evmorfopoulos
{"title":"A macromodel technique for VLSI dynamic simulation by mapping pre-characterized transitions","authors":"Dimitrios Bountas, G. Stamoulis, N. Evmorfopoulos","doi":"10.1109/ICCD.2008.4751900","DOIUrl":"https://doi.org/10.1109/ICCD.2008.4751900","url":null,"abstract":"Accurate simulation of digital circuits is an essential part of the design process. High precision models are generally used to confirm logic behavior and estimate power dissipation, which has become an extremely important design parameter. Unfortunately high precision analysis is expensive in computer execution time, and there is always a trade-off between accuracy and speed. This work proposes a new circuit simulation approach by storing a set of pre-characterized transition configurations for each standard library cell in a lookup table. The lookup table contains information about the voltage and the current transient waveform produced by SPICE simulation. The method achieves good accuracy levels for yielding the total or partial current waveform of a circuit in significantly less time compared to SPICE or other commercial tools.","PeriodicalId":345501,"journal":{"name":"2008 IEEE International Conference on Computer Design","volume":"454 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124308837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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