基于分段二次插值的函数逼近改进微结构

Shai Erez, G. Even
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引用次数: 1

摘要

提出了一种基于分段二次插值的函数求值微体系结构。微体系结构主要由一个查找表和两个乘法累加单元组成。先前基于分段二次插值的微架构已经被证明对小精度(例如,单精度)计算是有效的。此外,它们与分段线性插值一样快,而需要更小的表。我们的主要贡献是避免了在以前的微架构中出现的对额外的方形单元的需求。基于所提出的微结构,我们给出了单精度倒数近似(1/x)的详细设计。我们的设计基于两个乘法累加单元,其中包含截断的Booth基数4乘数。与以前使用二次插值的设计相比,该设计中的部分产品数量减少了20%以上。这种设计的延迟大约是19个全加法门的延迟,它可以很容易地流水线成两个阶段,每个阶段有10个全加法门的延迟。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An improved micro-architecture for function approximation using piecewise quadratic interpolation
We present a new micro-architecture for evaluating functions based on piecewise quadratic interpolation. The micro-architecture consists mainly of a look-up table and two multiply-accumulate units. Previous micro-architectures based on piecewise quadratic interpolation have been shown to be efficient for small precision (e.g., single precision) computations. Moreover, they are as fast as piecewise linear interpolation while requiring smaller tables. Our main contribution is in circumventing the need for the additional squaring unit that appears in previous micro-architectures. Based on the proposed micro-architecture, we present a detailed design of single precision reciprocal approximation (1/x). Our design is based on two multiply-accumulate units that contain truncated Booth radix 4 multipliers. The number of partial products in this design is reduced by over 20% compared to previous designs using quadratic interpolation. The latency of this design is roughly the delay of 19 full-adder gates, and it can be easily pipelined into two stages each with a delay of 10 full-adder gates.
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