{"title":"通过电路预处理改进基于sat的组合等效性检测","authors":"F. V. Andrade, L. M. Silva, A. O. Fernandes","doi":"10.1109/ICCD.2008.4751838","DOIUrl":null,"url":null,"abstract":"This paper presents a new implication tool (Vimplic) which can be used to improve SAT-based combinational equivalence checking. This tool quickly builds the implication graph of the miter circuit and traverse through it inferring implications among its nodes assignments. This set of implications and the miter circuit netlist are converted to conjunctive normal form (CNF) and submitted to the SAT solver in order to prove equivalence between the two circuits of the miter. Using Vimplic we have been able to dramatically reduce the overall verification time of several circuits outperforming the state-of-the-art techniques for CEC such as Berkmin561, NiVER, and C-SAT.","PeriodicalId":345501,"journal":{"name":"2008 IEEE International Conference on Computer Design","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"Improving SAT-based Combinational Equivalence Checking through circuit preprocessing\",\"authors\":\"F. V. Andrade, L. M. Silva, A. O. Fernandes\",\"doi\":\"10.1109/ICCD.2008.4751838\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a new implication tool (Vimplic) which can be used to improve SAT-based combinational equivalence checking. This tool quickly builds the implication graph of the miter circuit and traverse through it inferring implications among its nodes assignments. This set of implications and the miter circuit netlist are converted to conjunctive normal form (CNF) and submitted to the SAT solver in order to prove equivalence between the two circuits of the miter. Using Vimplic we have been able to dramatically reduce the overall verification time of several circuits outperforming the state-of-the-art techniques for CEC such as Berkmin561, NiVER, and C-SAT.\",\"PeriodicalId\":345501,\"journal\":{\"name\":\"2008 IEEE International Conference on Computer Design\",\"volume\":\"9 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 IEEE International Conference on Computer Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCD.2008.4751838\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE International Conference on Computer Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCD.2008.4751838","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Improving SAT-based Combinational Equivalence Checking through circuit preprocessing
This paper presents a new implication tool (Vimplic) which can be used to improve SAT-based combinational equivalence checking. This tool quickly builds the implication graph of the miter circuit and traverse through it inferring implications among its nodes assignments. This set of implications and the miter circuit netlist are converted to conjunctive normal form (CNF) and submitted to the SAT solver in order to prove equivalence between the two circuits of the miter. Using Vimplic we have been able to dramatically reduce the overall verification time of several circuits outperforming the state-of-the-art techniques for CEC such as Berkmin561, NiVER, and C-SAT.