{"title":"Hardware method for context searching in intelligent secondary memory","authors":"J. J. R. Ortiz","doi":"10.1049/IJ-CDT:19790048","DOIUrl":"https://doi.org/10.1049/IJ-CDT:19790048","url":null,"abstract":"Considerable interest has recently evolved in the development of machines for searching large databases. The study of architectures for these machines has combined the studies of associative memories, intelligent secondary memories and database management systems. The term, nonnumeric architecture has been given to this study. Unlike the Von Neuman architecture, which is based on a numeric operator, this new architecture will be oriented to searching operations.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115211427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Speed-independent asynchronous arbiter","authors":"P. Corsini","doi":"10.1049/IJ-CDT:19790047","DOIUrl":"https://doi.org/10.1049/IJ-CDT:19790047","url":null,"abstract":"A very simple asynchronous arbiter is given for n concurrent asynchronous processors interconnected in a speed-independent way. The arbiter consists of one inverter and n identical modules each incorporating a recently described 2-user arbiter.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130403347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Detection of symmetries in totally specified or partially specified combinational functions","authors":"D. M. Miller, J. Muzio","doi":"10.1049/IJ-CDT.1979.0043","DOIUrl":"https://doi.org/10.1049/IJ-CDT.1979.0043","url":null,"abstract":"A method for the detection of symmetries in combinational functions is presented. A comprehensive range of symmetries is allowed. Complete symmetry in all input variables is merely a special case. The method presented is applicable to both totally specified and partially specified functions.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131852378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Testing digital circuits: guidelines for research","authors":"R. Bennetts","doi":"10.1049/IJ-CDT:19790038","DOIUrl":"https://doi.org/10.1049/IJ-CDT:19790038","url":null,"abstract":"Part of the duties of those who publish is to pass judgement on the written submissions of those who aspire to publish. This is not an enviable task, but does have the advantage of allowing early access to the results of useful research. Unfortunately, as the Editors of this and other journals will testify, much of what is submitted for publication is rejected initially, usually for reasons connected with the presentation or correctness of detail. My writing of this editorial has been prompted by a recent refereeing exercise, and my aim is to comment on another possible reason for rejection, the relevance of the work. The area I address myself to is that of digital-circuit testing, and the paper is question was describing yet another procedure for generating test patterns for irredundant combinational-logic circuits. Irrespective of the fact that, academically at least, it was interesting, the basic question arose: is this still a problem area? We know that, in practice, very few circuits are wholly combinational and also that algorithms of the 'D-algorithm' type (The D-algorithm occurs in many disguises) are well able to handle such circuits when they do occur. There can be no real justification, therefore, for continuing to study this problem when other important and intellectually more demanding problems exist with modern l.s.i. and v.l.s.i. boards. What are these problems? To answer this question one has to become intimately concerned with the whole process of producing test patterns for practical designs and I have had the opportunity to do this over the last few months. The following comments are therefore based largely on this experience and indicate what I think are more profitable avenues for research workers to pursue. I have put these comments into three broad categories of test-pattern generation, evaluation, and application and I would not claim that the list of research topics is exhaustive.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128730884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Systematic method of searching for minimum generalised Reed-Muller forms using a variable state function","authors":"Z. Lotfi, A. Tosser","doi":"10.1049/IJ-CDT:19790045","DOIUrl":"https://doi.org/10.1049/IJ-CDT:19790045","url":null,"abstract":"A binary function of the state of any variable is introduced to calculate the number of terms obtained by a generalised Reed-Muller expansion of a sum of minterms. A systematic method of searching for the minimum Reed-Muller form is thus available.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121609358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Programmable, digital speech synthesiser","authors":"R. Linggard, F. Marlow","doi":"10.1049/IJ-CDT.1979.0040","DOIUrl":"https://doi.org/10.1049/IJ-CDT.1979.0040","url":null,"abstract":"A low-cost, programmable, digital speech synthesiser, to be used for research purposes, is described. This machine has a general-purpose architecture of arithmetic unit, memory and control unit, which enables it to simulate formant-type synthesisers as well as vocal-tract models, all in real time. The principle virtue of the machine is the ease with which changes in the structure of a synthesiser can be evaluated, thus facilitating the rapid optimisation of a proposed design.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114828849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Book review: System Design with Microprocessors","authors":"D. Noaks","doi":"10.1049/IJ-CDT:19790044","DOIUrl":"https://doi.org/10.1049/IJ-CDT:19790044","url":null,"abstract":"","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124093395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Use of memories and programmable logic arrays for asynchronous sequential circuits","authors":"A. Ditzinger, H. Lipp","doi":"10.1049/IJ-CDT:19790046","DOIUrl":"https://doi.org/10.1049/IJ-CDT:19790046","url":null,"abstract":"The design of asynchronous sequential circuits is commonly related to the problem of observing some specific timing constraints to avoid unreliable behaviour. State assignment and hazard-free construction of the combinational circuits for the state transition equations are the most essential topics to investigate. They contribute significantly to the design, particularly in comparison with that of synchronously operated systems. On the other hand, the application of digital circuitry for solving control tasks implies more and more asynchronous interaction between the controller and the controlled unit, and also the use of modern, highly-integrated modules. This paper investigates the possibility of applying arbitrarily chosen, but unique, codes for state assignments, using l.s.i. memories and programmable logic arrays for implementing more complex asynchronous sequential circuits than is possible with discrete or s.s.i/m.s.i. components. A basic model is derived to describe the time properties of such matrix arrays, and design rules are established to decide easily by some simple measurements, if a given module may be used in that application. The results of a broad investigation into available memories and field-programmable logic arrays show that reliable asynchronous sequential circuits may be implemented without having hazard problems and the need for special state-assignment procedures.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"216 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128168653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Book review: Principles of Digital Communication and Coding","authors":"D. Ingram","doi":"10.1049/ij-cdt:19790042","DOIUrl":"https://doi.org/10.1049/ij-cdt:19790042","url":null,"abstract":"","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114329012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Study of the use of microprocessors in digital filtering","authors":"B. Farhang-Boroujeny, G. J. Hawkins","doi":"10.1049/IJ-CDT:19790032","DOIUrl":"https://doi.org/10.1049/IJ-CDT:19790032","url":null,"abstract":"In this paper, the application of microprocessors to digital filtering has been considered. To achieve the highest possible working frequencies when using microprocessors it has been found necessary to employ the method of distributed arithmetic. A new computational formulation is introduced which leads to methods of implementation which allow for better signal/roundoff-noise ratios at the expense of a few extra instructions in the iterative loops; this causes only a slight decrease from the optimum working frequencies. Also, the addition of bias values to precomputed constants is shown to lead to some improvement to the signal/roundoff-noise. These improvements have been verified by means of computer simulations. The methods suggested can be implemented by employing microprocessors with some dedicated hardware, and this helps to reduce the processing time. The employment of various facilities available on some microprocessors is considered, and tests have been carried out on a sample processor.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123142666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}