Testing digital circuits: guidelines for research

Part of the duties of those who publish is to pass judgement on the written submissions of those who aspire to publish. This is not an enviable task, but does have the advantage of allowing early access to the results of useful research. Unfortunately, as the Editors of this and other journals will testify, much of what is submitted for publication is rejected initially, usually for reasons connected with the presentation or correctness of detail. My writing of this editorial has been prompted by a recent refereeing exercise, and my aim is to comment on another possible reason for rejection, the relevance of the work. The area I address myself to is that of digital-circuit testing, and the paper is question was describing yet another procedure for generating test patterns for irredundant combinational-logic circuits. Irrespective of the fact that, academically at least, it was interesting, the basic question arose: is this still a problem area? We know that, in practice, very few circuits are wholly combinational and also that algorithms of the 'D-algorithm' type (The D-algorithm occurs in many disguises) are well able to handle such circuits when they do occur. There can be no real justification, therefore, for continuing to study this problem when other important and intellectually more demanding problems exist with modern l.s.i. and v.l.s.i. boards. What are these problems? To answer this question one has to become intimately concerned with the whole process of producing test patterns for practical designs and I have had the opportunity to do this over the last few months. The following comments are therefore based largely on this experience and indicate what I think are more profitable avenues for research workers to pursue. I have put these comments into three broad categories of test-pattern generation, evaluation, and application and I would not claim that the list of research topics is exhaustive.