{"title":"与速度无关的异步仲裁器","authors":"P. Corsini","doi":"10.1049/IJ-CDT:19790047","DOIUrl":null,"url":null,"abstract":"A very simple asynchronous arbiter is given for n concurrent asynchronous processors interconnected in a speed-independent way. The arbiter consists of one inverter and n identical modules each incorporating a recently described 2-user arbiter.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1979-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Speed-independent asynchronous arbiter\",\"authors\":\"P. Corsini\",\"doi\":\"10.1049/IJ-CDT:19790047\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A very simple asynchronous arbiter is given for n concurrent asynchronous processors interconnected in a speed-independent way. The arbiter consists of one inverter and n identical modules each incorporating a recently described 2-user arbiter.\",\"PeriodicalId\":344610,\"journal\":{\"name\":\"Iee Journal on Computers and Digital Techniques\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1979-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Iee Journal on Computers and Digital Techniques\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1049/IJ-CDT:19790047\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Iee Journal on Computers and Digital Techniques","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1049/IJ-CDT:19790047","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A very simple asynchronous arbiter is given for n concurrent asynchronous processors interconnected in a speed-independent way. The arbiter consists of one inverter and n identical modules each incorporating a recently described 2-user arbiter.
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