{"title":"Design of NAND Logic Gate Using a Single Molecule Transistor","authors":"A. Nasri, A. Boubaker, W. Khaldi, A. Kalboussi","doi":"10.1109/DTSS.2019.8915350","DOIUrl":"https://doi.org/10.1109/DTSS.2019.8915350","url":null,"abstract":"Here we propose to study the I-V characteristics of the three-terminal molecular devices. The 1.4-Benzenedithiol-Molecular Field Effect Transistor (MFET) model is implemented using Matlab simulator. The modeling results showed good performance. In addition, we used our model under VHDL-AMS to create a logic gate. Specifically, we discussed in detail the operation principle of molecular NAND logic gate.","PeriodicalId":342516,"journal":{"name":"2019 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125575104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of Low Cost Cognitive Radio Platform for Demonstration and Testing Purposes","authors":"Moatz M. Bahgat","doi":"10.1109/DTSS.2019.8915089","DOIUrl":"https://doi.org/10.1109/DTSS.2019.8915089","url":null,"abstract":"Nowadays, wireless communication systems play an important role in our daily life. One of the most prominent wireless communications technologies is known as the cognitive radio technology. Cognitive radio is expected to be the next disruptive radio communication technology due to the fact that it may solve and overcome many of the issues affecting the current wireless communication systems. In order to understand how a cognitive radio system, subsystem, or algorithm behaves in realistic scenarios, an experimental platform is required. This paper presents a new design for a cognitive radio platform. The foremost objective of the novel design approach followed in developing the presented topic is to offer a low-cost and low-power solution that simplifies the demonstration and testing of cognitive radio communications.","PeriodicalId":342516,"journal":{"name":"2019 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"198 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116485578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Dahmani, I. Zaaroura, P. Campistron, J. Carlier, M. Toubal, B. Nongaillard
{"title":"study of a dual longitudinal and shear acoustic wave ZnO transducer in the gigahertz frequency range: application to viscosity measurement and first step for device integration","authors":"H. Dahmani, I. Zaaroura, P. Campistron, J. Carlier, M. Toubal, B. Nongaillard","doi":"10.1109/DTSS.2019.8914906","DOIUrl":"https://doi.org/10.1109/DTSS.2019.8914906","url":null,"abstract":"In this paper, we study a high frequency (~1GHz) ZnO transducer integrated within a silicon substrate, which generates in the same area, a compressional and a shear acoustic wave. These two kinds of waves can be used to characterize fluid-solid interfaces' properties in the same microscopic area and at the same time from the longitudinal and the shear reflection coefficients [1], [2]. The principle will be explained and validated using RF microprober. With this in mind, the shear and volume viscosity of a drop of water will be presented. Finally, we will propose a first example of electrical matching of the transducer in this high frequency range in order to promote, first, the longitudinal wave.","PeriodicalId":342516,"journal":{"name":"2019 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131017139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of Low Power Discrete Time FF ΔΣ Modulator for Biomedical Application","authors":"D. Laouej, H. Daoud, J. Mallek, M. Loulou","doi":"10.1109/DTSS.2019.8915250","DOIUrl":"https://doi.org/10.1109/DTSS.2019.8915250","url":null,"abstract":"High speed, low voltage delta-sigma (ΔΣ) analog to digital converter (ADC) is required for low power medical applications. A second order discrete time (DT) feed forward (FF) ΔΣ modulator with very low power consumption is presented in this paper. The OTA is the key building block and the most power-hungry circuit for ΔΣ modulator design. Using TSMC 0.18μm CMOS technology, the telescopic OTA is optimized using the practical swarm optimization (PSO) algorithm; it achieves a DC gain of 62dB, a GBW of 166.6MHz and it consumes only 35μW. The optimized FF ΔΣ modulator has been implemented with an OSR of 50, a signal bandwidth of 0.5MHz and a sampling frequency of 50MHz. The designed modulator is suitable for low medical application in 2.4GHz ISM band for IEEE 802.15.1/Bluetooth standard. This circuit attains a peak SNR of 52dB and a resolution of 8,34bits. This topology consumes only 71μW under 1.8V supply voltage.","PeriodicalId":342516,"journal":{"name":"2019 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134394837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fault Attacks Resistant AES Hardware Implementation","authors":"H. Mestiri, N. Benhadjyoussef, M. Machhout","doi":"10.1109/DTSS.2019.8914979","DOIUrl":"https://doi.org/10.1109/DTSS.2019.8914979","url":null,"abstract":"The protection of the symmetric cryptographic algorithm, specially the Advanced Encryption Standard (AES), against fault injection attacks is very inportant to guarantee the security of transmitted data. In this paper, we proposed a new fault detection scheme based information redundancy for the AES. We analysis the detection scheme robustness against the fault injection attacks. The simulation fault attacks results prove that the fault coverage reaches 71.43%. In addition, the original and the protected AES hardware implementation have been implemented on the Xilinx Virtex-5 FPGA. We confirm that the protected AES is very effective while keeping the frequency overhead very low.","PeriodicalId":342516,"journal":{"name":"2019 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132039752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fast and Accurate Simulation of Ultrascaled Carbon Nanotube Field-Effect Transistor Using ANN Sub-Modeling Technique","authors":"K. Tamersit, F. Djeffal","doi":"10.1109/DTSS.2019.8915240","DOIUrl":"https://doi.org/10.1109/DTSS.2019.8915240","url":null,"abstract":"In this paper, we have proposed a new modeling methodology based on the artificial neural networks (ANN) to simulate the ultra-scaled carbon nanotube field-effect transistor (CNTFET). The sub-modeling concept has been employed to efficiently simplify the overall modeling process. The developed sub-models have been compared with the mode space nonequilibrium Green's function (MS-NEGF) simulations in terms of the resulted drain current, where a good agreement has been recorded. In addition, simulation tests have shown that the proposed smart models are faster of about two order of magnitude over the standard MS-NEGF simulation. The obtained results indicate that the proposed ANN-based sub-modeling is an accurate and computationally efficient approach, which can be successfully used to simulate, analyze, and optimize the ultra-scaled CNTFETs and the futuristic CNT-based nanoscale integrated circuits.","PeriodicalId":342516,"journal":{"name":"2019 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124115328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Aicha Boujnah, A. Boubaker, A. Kalboussi, Shou Li, K. Lmimouni
{"title":"Numerical Studies and Validation of Experimental Pentacene Transistor Characteristics","authors":"Aicha Boujnah, A. Boubaker, A. Kalboussi, Shou Li, K. Lmimouni","doi":"10.1109/DTSS.2019.8915324","DOIUrl":"https://doi.org/10.1109/DTSS.2019.8915324","url":null,"abstract":"This paper present a numerical validation of experimental results of Bottom Gate/Bottom Contact Pentacene transistor using SILVACO ATLAS simulator. We investigated the impact of different gate dielectric thickness on transistor performance and we estimated threshold voltage Vth, current ratio Ion/Ioff and saturation mobility μ values. We found that gate dielectric thickness is proportional to Vth and inversely proportional to μ.","PeriodicalId":342516,"journal":{"name":"2019 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130732571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Bouzid, M. Mbarki, C. Dridi, Mohamed Nazih Omri
{"title":"Smart Adaptable Indoor Lighting System (SAILS)","authors":"S. Bouzid, M. Mbarki, C. Dridi, Mohamed Nazih Omri","doi":"10.1109/DTSS.2019.8915261","DOIUrl":"https://doi.org/10.1109/DTSS.2019.8915261","url":null,"abstract":"The issue of saving energy is the main incentive in many researches. Lighting is the main factor contributing to these problems is lighting. Its costs to be covered by local municipality are heavy. The aim of this work is to propose a smart adaptable lighting system. In particular, we proposed an approach that generates in an intelligent way all possible lighting strategies according to user preferences while respecting lighting norms. Moreover, our automated system control light level to save energy. It dims lighting sources to maintain a required level when needed according to space occupation and light intensity level. Moreover, it detects nodes failure and overcomes resulting lack. Our system implements energy efficient technologies as ZigBee and LEDs. It monitors sensors and lighting sources states in real-time. To assess the usefulness of our system, we compared our system to other works. Experimental results show that it saves remarkable power, which can reach 77%, as compared to conventional systems without sensors and without an intelligent system.","PeriodicalId":342516,"journal":{"name":"2019 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"49 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113989140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Electrical characterizations of Schottky diode with zinc oxide nanowires","authors":"Ahlem Rouis, N. Hizem, A. Kalboussi","doi":"10.1109/DTSS.2019.8915051","DOIUrl":"https://doi.org/10.1109/DTSS.2019.8915051","url":null,"abstract":"This paper presents an in-depth analysis of the I (V) and I(V-T) characteristics of the Schottky Pt / ZnO nanowire diode. Detailed analyzes were performed to extract the various electrical parameters and information on the interface states. The characteristic parameters of the structure such as barrier height, ideality factor, saturation current and series resistance were determined from the current-voltage measurement. The ideality factor (3.58) value at room temperature is higher than unity probably due to the presence of the n-ZnO / p-Si heterojunction in series with the Pt / ZnO nanowire. The value of the computed barrier height of the diode (0.65 eV) using the thermionic emission model is in good agreement with the theoretically predicted value. Indeed, these two values obtained by the current-voltage I(V) characteristics suggested the presence of interface states between the Pt and the nanowire ZnO. To confirm this observation, we carried out the measurement C (V).","PeriodicalId":342516,"journal":{"name":"2019 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117306733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Mouna Bedoui, B. Bouallegue, B. Hamdi, M. Machhout
{"title":"An Efficient Fault Detection Method for Elliptic Curve Scalar Multiplication Montgomery Algorithm","authors":"Mouna Bedoui, B. Bouallegue, B. Hamdi, M. Machhout","doi":"10.1109/DTSS.2019.8914743","DOIUrl":"https://doi.org/10.1109/DTSS.2019.8914743","url":null,"abstract":"Elliptical curve cryptography (ECC) is being used more and more in public key cryptosystems. Its main advantage is that, at a given security level, key sizes are much smaller compared to classical asymmetric cryptosystems like RSA. Smaller keys imply less power consumption, less cryptographic computation and require less memory. Besides performance, security is another major problem in embedded devices. Cryptosystems, like ECC, that are considered mathematically secure, are not necessarily considered safe when implemented in practice. An attacker can monitor these interactions in order to mount attacks called fault attacks. A number of countermeasures have been developed to protect Montgomery Scalar Multiplication algorithm against fault attacks. In this work, we proposed an efficient countermeasure premised on duplication scheme and the scrambling technique for Montgomery Scalar Multiplication algorithm against fault attacks. Our approach is simple and easy to hardware implementation. In addition, we perform injection-based error simulations and demonstrate that the error coverage is about 99.996%.","PeriodicalId":342516,"journal":{"name":"2019 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128962518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}