Fault Attacks Resistant AES Hardware Implementation

Abstract

The protection of the symmetric cryptographic algorithm, specially the Advanced Encryption Standard (AES), against fault injection attacks is very inportant to guarantee the security of transmitted data. In this paper, we proposed a new fault detection scheme based information redundancy for the AES. We analysis the detection scheme robustness against the fault injection attacks. The simulation fault attacks results prove that the fault coverage reaches 71.43%. In addition, the original and the protected AES hardware implementation have been implemented on the Xilinx Virtex-5 FPGA. We confirm that the protected AES is very effective while keeping the frequency overhead very low.