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Towards Easy-to-Use Checkpointing of MPI Applications within CLUSTERIX 在CLUSTERIX中实现易于使用的MPI应用程序检查点
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.72
P. Czarnul, Arkadiusz Urbaniak, M. Fraczak, Maciej Dyczkowski, B. Balcerek
{"title":"Towards Easy-to-Use Checkpointing of MPI Applications within CLUSTERIX","authors":"P. Czarnul, Arkadiusz Urbaniak, M. Fraczak, Maciej Dyczkowski, B. Balcerek","doi":"10.1109/PCEE.2004.72","DOIUrl":"https://doi.org/10.1109/PCEE.2004.72","url":null,"abstract":"While there exist many kernel and user level libraries/systems which support checkpointing working processes and resuming their operations, it is still very difficult to provide an easy-to-use tool to assist checkpointing parallel applications. In this work, we aim at the development of an easy-to-use user-guided library to support checkpointing parallel MPI applications to be executed within the CLUSTERIX environment i.e. a collection of distributed HPC clusters. We propose a programmer-assisted approach with process state packing and unpacking at the code level for SPMD HPC applications. Although the library is in its early stage of development we present checkpoint/restart times and application execution (interrupted by checkpointing) times for the proposed approach compared to the same application linked with the ckpt user level library.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116924058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Parallel Implementation of FDTD Computations Based on Macro Data Flow Paradigm 基于宏数据流范式的FDTD计算并行实现
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.52
A. Smyk, M. Tudruj
{"title":"Parallel Implementation of FDTD Computations Based on Macro Data Flow Paradigm","authors":"A. Smyk, M. Tudruj","doi":"10.1109/PCEE.2004.52","DOIUrl":"https://doi.org/10.1109/PCEE.2004.52","url":null,"abstract":"In this paper, we present a methodology, which enables designing optimal macro data flow graphs that represent computation and communication patterns for the FDTD problem in irregular computational areas. The macro data flow graphs are executed in a MIMD system. Communication is implemented with a Remote Direct Memory Access facility. To obtain minimal communication overheads, the rotating buffers mechanism has been introduced. It is used to control (and synchronize) data flow during execution of fine grain applications with irregular communication. Several methods for data flow graph partitioning and merging are presented. In these methods we take into consideration both computational load balance and minimal communication overhead. Experimental results obtained by simulations are discussed.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127308001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Providing a High-Performance VIA-Module for LAM/MPI 为LAM/MPI提供了一个高性能的通过模块
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.59
Torsten Mehlan, W. Rehm, R. Engler, Tobias Wenzel
{"title":"Providing a High-Performance VIA-Module for LAM/MPI","authors":"Torsten Mehlan, W. Rehm, R. Engler, Tobias Wenzel","doi":"10.1109/PCEE.2004.59","DOIUrl":"https://doi.org/10.1109/PCEE.2004.59","url":null,"abstract":"The Virtual Interface Architecture (VIA) was introduced to define a common set of features that are suitable to build high-speed networks. Today the interface of VIA serves as access point to a wide range of system area networks. M-VIA is a software that provides the VIA interface on top of several Ethernet cards. The overhead of TCP/IP protocols is avoided by running M-VIA. To benefit from this performance we developed a LAM/MPI module that utilizes VIA functions to transmit data. The key concepts of data transmission and memory management are presented by this paper. Furthermore a comparative performance analysis is included.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114168379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Dynamic Piecewise Linear/Regular Algorithms 动态分段线性/正则算法
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.28
Frank Hannig, J. Teich
{"title":"Dynamic Piecewise Linear/Regular Algorithms","authors":"Frank Hannig, J. Teich","doi":"10.1109/PCEE.2004.28","DOIUrl":"https://doi.org/10.1109/PCEE.2004.28","url":null,"abstract":"In this paper we present an extension of the class of piecewise linear algorithms (PLAs) in order to model one type of dynamic data dependencies. This extension significantly increases the range of applications which can be parallelized and mapped to massively parallel processor arrays. For instance, a lot of computational intensive applications for video and image processing consist of nested loop programs with only few and simple run-time dependent conditionals. Furthermore, we outline in which case these extensions can directly used - with slight changes - within traditional mapping methodologies based on loop parallelization in the polytope model. Additionally, we outline future research directions in the case existing methods will be inefficient.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133917149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
An Analog VLSI Pulsed Neural Network Implementation for Image Segmentation 用于图像分割的模拟VLSI脉冲神经网络实现
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.11
D. Matolin, J. Schreiter, S. Getzlaff, R. Schüffny
{"title":"An Analog VLSI Pulsed Neural Network Implementation for Image Segmentation","authors":"D. Matolin, J. Schreiter, S. Getzlaff, R. Schüffny","doi":"10.1109/PCEE.2004.11","DOIUrl":"https://doi.org/10.1109/PCEE.2004.11","url":null,"abstract":"We present a massively parallel VLSI realisation of a pulse-coupled neural network for image segmentation. The network consists of simple integrate-and-fire (IAF) neurons with self-organising local connections. The prototype implementation comprises 64 x 64 neurons with coupling of four nearest neighbours, digital to analog converters, analog memories and a digital readout circuit. The chip has been fabricated in a 0.35μm standard CMOS technology.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130544949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
An EM Algorithm for Fitting of Real Traffic Traces to PH-Distribution 真实交通轨迹拟合ph分布的EM算法
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.12
P. Buchholz, A. Panchenko
{"title":"An EM Algorithm for Fitting of Real Traffic Traces to PH-Distribution","authors":"P. Buchholz, A. Panchenko","doi":"10.1109/PCEE.2004.12","DOIUrl":"https://doi.org/10.1109/PCEE.2004.12","url":null,"abstract":"In this paper we present an algorithm of the EM-type that performs fitting of PH-distributions with a given number of states to empirical distribution. In contrast to known approaches, the algorithm first generates a discretized representation of the observed data and then performs the fitting. In this way the algorithm is more efficient than other known EM-type methods. By an appropriate discretization, the main part as well as the tail of the distribution can be approximated sufficiently accurate.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129761711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Influence of Exception Handling on Distributed Applications 异常处理对分布式应用程序的影响
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.38
P. Kaczmarek, H. Krawczyk
{"title":"Influence of Exception Handling on Distributed Applications","authors":"P. Kaczmarek, H. Krawczyk","doi":"10.1109/PCEE.2004.38","DOIUrl":"https://doi.org/10.1109/PCEE.2004.38","url":null,"abstract":"The paper presents a methodology of assessment of distributed systems in the presence of exceptions and errors. The analysis is done by identifying data transitions for a system and deriving general characteristics about system behavior. Additionally, characteristics of internal subsystems are calculated. Distributed dependencies are modeled as basic dependencies between methods and compound dependencies existing in the system. The analysis answers the question how distributed interactions influence the result of execution, which supports the identification of correct programming constructs. The theoretical model is used in a developed tool that allows to automatically modify, trace and analyze distributed applications. Additionally, a simulator is developed to estimate the behavior of a real system. An example of experimental use of the methodology is presented.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129280603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Automatic Code Generation for SIMD DSP Architectures: An Algebraic Approach SIMD DSP架构的自动代码生成:一种代数方法
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.17
P. Robelly, G. Cichon, H. Seidel, G. Fettweis
{"title":"Automatic Code Generation for SIMD DSP Architectures: An Algebraic Approach","authors":"P. Robelly, G. Cichon, H. Seidel, G. Fettweis","doi":"10.1109/PCEE.2004.17","DOIUrl":"https://doi.org/10.1109/PCEE.2004.17","url":null,"abstract":"Driven by the ever increasing algorithm complexity on the field of mobile communications systems, SIMD DSP architectures have emerged as an approach that offers the necessary processing power at reasonable levels of die size and power consumption. However, this kind of DSP architectures imposes new challenges for programmers, since algorithms have to be designed to exploit the available parallelism on the processor. Taking as a starting point an algebraic framework that captures the SIMD computational model, we report in this paper about our efforts to design and automatically generate object code for our family of DSP architectures independent of the available SIMD parallelism. We show how these algebraic structures can be used as a high level programming language that offers a unified approach to design and describe algorithms using SIMD parallelism. Moreover, we show how these algebraic structures offer concise rules for the automatic code generation.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123537532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Associative Graph Processor and Its Properties 关联图处理器及其性质
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.15
A. Nepomniaschaya, Zbigniew Kokosinski
{"title":"Associative Graph Processor and Its Properties","authors":"A. Nepomniaschaya, Zbigniew Kokosinski","doi":"10.1109/PCEE.2004.15","DOIUrl":"https://doi.org/10.1109/PCEE.2004.15","url":null,"abstract":"In this paper a model of a versatile associative graph processor called AGP is proposed. The model can work both in bit-serial and in bit-parallel mode and enables simultaneous search for a set of comparands and selection of the search types. In addition it has some built-in operations designed for associative graph algorithms. The selected functions and basic procedures of this model are described and its possible architecture is discussed.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132693892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
The Cellular Automata Network Compiler System: Modules and Features 元胞自动机网络编译系统:模块和特征
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.67
Claudia Roberta Calidonna, M. Furnari
{"title":"The Cellular Automata Network Compiler System: Modules and Features","authors":"Claudia Roberta Calidonna, M. Furnari","doi":"10.1109/PCEE.2004.67","DOIUrl":"https://doi.org/10.1109/PCEE.2004.67","url":null,"abstract":"In simulating complex phenomena by Cellular Automata (CA) programming model performances assume a crucial role. The efficient exploitation of intrinsic parallelism is a must for this kind of applications. The Cellular Automata Network (CAN) model, that is an extension of the CA classical model due to the introduction of the network abstraction between automata nodes, offer another parallelism source besides to the classical CA parallelism source. In order to exploit efficiently this opportunities tools and systems must be designed. In this paper we deal with the CAN compiler system components description and features designed ad hoc.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133896016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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