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FIT - A Parallel Hierarchical Fault Simulation Environment FIT -一个并行分层故障仿真环境
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.34
S. Misera, H. Vierhaus
{"title":"FIT - A Parallel Hierarchical Fault Simulation Environment","authors":"S. Misera, H. Vierhaus","doi":"10.1109/PCEE.2004.34","DOIUrl":"https://doi.org/10.1109/PCEE.2004.34","url":null,"abstract":"Systems on a chip (SoCs) that consist of one or several processor devices, other complex functional blocks, embedded memories plus multiple interconnects are a big challenge to design and test technology. The simulation of such complex systems under fault conditions is an open problem, since RTL simulators typically do not provide simple means of fault injection and high speed in combination. On the other hand, advance fault simulation tools are be required to validate circuit architectures that provide online test and error correction. The work presented here describes the first version of a hierarchical and parallel fault simulation tool that was developed to validate self-test and error correction circuits on SoCs.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"86 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120981564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Optimal Programming of Critical Sections in Modern Network Processors under Performance Requirements 现代网络处理器在性能要求下的关键截面优化规划
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.47
H. Krawczyk, Tomasz Madajczak
{"title":"Optimal Programming of Critical Sections in Modern Network Processors under Performance Requirements","authors":"H. Krawczyk, Tomasz Madajczak","doi":"10.1109/PCEE.2004.47","DOIUrl":"https://doi.org/10.1109/PCEE.2004.47","url":null,"abstract":"Modern network processors deliver a set of methods for implementing critical sections. A number of them rely on specific hardware support and capabilities, while software techniques are still available when hardware support is not flexible enough. Network processors are dedicated to packet processing and their main goal is to achieve the best possible packet processing performance. Therefore, when choosing the implementation method for a particular problem that will be protected by a critical section, the aim must me for the method to influence the overall system performance A wrongly implemented critical section can very easily degrade the level of parallelism and in consequence the performance of the whole system. Sometimes even correctly implemented critical sections can negatively impact the speed of paths that do not need to be protected with a critical section.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127234054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Computing Passive Reduced-Order Models for Circuit Simulation 电路仿真中无源降阶模型的计算
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.21
P. Benner, E. S. Quintana‐Ortí, G. Quintana-Ortí
{"title":"Computing Passive Reduced-Order Models for Circuit Simulation","authors":"P. Benner, E. S. Quintana‐Ortí, G. Quintana-Ortí","doi":"10.1109/PCEE.2004.21","DOIUrl":"https://doi.org/10.1109/PCEE.2004.21","url":null,"abstract":"We investigate numerical methods for passive model reduction of linear dynamical systems. This is an important task in circuit simulation when modeling parasitic effects of interconnect. We will show how positive real balancing, based on balancing the solutions of two algebraic Riccati equations, can be used for passive model reduction of large-scale systems on parallel computers. Numerical experiments demonstrate the performance of the parallel algorithms using several examples from circuit simulation.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127235468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Limits of the Distributed Finite Element Time Domain Algorithm in Multi-Computer Environment 分布式有限元时域算法在多机环境下的局限性
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.41
B. Butrylo, C. Vollaire, L. Nicolas
{"title":"Limits of the Distributed Finite Element Time Domain Algorithm in Multi-Computer Environment","authors":"B. Butrylo, C. Vollaire, L. Nicolas","doi":"10.1109/PCEE.2004.41","DOIUrl":"https://doi.org/10.1109/PCEE.2004.41","url":null,"abstract":"This paper deals with a concurrent version of the finite element time domain method. The algorithm works in SPMD mode and is executed in the MPI distributed environment. Its properties are validated with some different multi-computer, loosely coupled platforms. The real value and approximated asymptotic values of the basic metrics of speedup are presented and discussed.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122424044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Numerical Evaluation of Linear Recurrences on High Performance Computers and Clusters of Workstations 线性递归在高性能计算机和工作站集群上的数值评价
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.46
Przemysław Stpiczyński
{"title":"Numerical Evaluation of Linear Recurrences on High Performance Computers and Clusters of Workstations","authors":"Przemysław Stpiczyński","doi":"10.1109/PCEE.2004.46","DOIUrl":"https://doi.org/10.1109/PCEE.2004.46","url":null,"abstract":"The aim of this paper is to show that the recently developed algorithm for solving linear recurrence systems on shared-memory parallel computers can be efficiently implemented on high performance message passing parallel and vector computers and clusters of workstations. We analyze the performance of the algorithm using two well known models: BSP and Hockney-Jesshope. Finally, we present the results of experiments performed of a Cray X1 and cluster of 15 personal computers running under Linux.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131550061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An Optimal Abstraction Model for Hardware Multithreading in Modern Processor Architectures 现代处理器体系结构中硬件多线程的最优抽象模型
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.13
Tomasz Madajczak
{"title":"An Optimal Abstraction Model for Hardware Multithreading in Modern Processor Architectures","authors":"Tomasz Madajczak","doi":"10.1109/PCEE.2004.13","DOIUrl":"https://doi.org/10.1109/PCEE.2004.13","url":null,"abstract":"This document presents a theoretical analysis of state-of-the-art hardware threading approaches such as Switch on Event Multi Threading (SoEMT) and Simultaneous Multi Threading (SMT). It proposes that the On-Demand Virtual Single-Instruction-Multiple-Data (ODVSIMD) abstraction model is a very efficient method of hardware threading in certain scenarios. The principles of ODVSIMD abstraction model are defined. Then, there is a proposition of the application for this abstraction model that is the data-driven automated loop partitioning. The document shows how the DOALL and DOACROSS loops can be parallelized with auto-partitioning to the ODVSIMD abstraction. This document then presents the results of parallel execution of both loop types. The results are obtained with a worksheet simulation. The document also discusses the main differences between SoEMT and SMT architectures in the context achievable performance.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124808251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Fault-Tolerant Voting Scheme for Multithreaded Environments 多线程环境下的容错投票方案
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.2
Bernhard Fechner, J. Keller
{"title":"A Fault-Tolerant Voting Scheme for Multithreaded Environments","authors":"Bernhard Fechner, J. Keller","doi":"10.1109/PCEE.2004.2","DOIUrl":"https://doi.org/10.1109/PCEE.2004.2","url":null,"abstract":"Voting schemes are widely used in fault-tolerant systems, mainly systems which imply temporal or component redundancy. We present a voting scheme for multithreaded environments which is based on the observation that a fault-tolerant system which does not know its history can not distinguish between transient (SEUs) and permanent errors, caused by use of a faulty component. The history of errors is used to predict future errors and to determine if a permanent or transient error occurred. Only in the former case a repair is necessary; in the latter case recovery is sufficient. Using prediction and credibility points we are able to tell if a system failure is likely to occur soon. The more credibility a version has, the more likely it will compute a correct result. Therefore we can use credibility points in connection with thread priorisation to increase performance.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130858764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A PC-Based Real-Time Parallel Simulator of Electric Systems and Drives 基于pc的电力系统与驱动实时并行模拟器
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.8
C. Dufour, J. Bélanger
{"title":"A PC-Based Real-Time Parallel Simulator of Electric Systems and Drives","authors":"C. Dufour, J. Bélanger","doi":"10.1109/PCEE.2004.8","DOIUrl":"https://doi.org/10.1109/PCEE.2004.8","url":null,"abstract":"This paper presents the RT-LAB Electrical Drive Simulator technology along with practical applications. The RT-LAB[Opal-RT Technologies inc.] simulation software enables the parallel simulation of electrical circuit on clusters of PC running QNX or RT-Linux operating systems at sample time below 10 µs. Using standard Simulink models including SimPowerSystems models, RT-LAB build computation and communication tasks necessary to effectively make parallel simulation of electrical systems on low cost off-the-shelf PC technology. To accommodate the high bandwidth of electrical systems, the RT-LAB Electrical Drive Simulator comes with special Simulink-based modelisation tools, namely ARTEMIS[Opal-RT Technologies Inc.] and RT-Events[Opal-RT Technologies Inc.], that permits real-time simulation of electrical systems at practical time step of 10 µs but with sub-µs equivalent precision through the use of interpolation techniques.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123082916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 52
Estimating Dependability of Parallel FFT Application using Fault Injection 用故障注入估计并行FFT应用的可靠性
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.32
A. Derezińska
{"title":"Estimating Dependability of Parallel FFT Application using Fault Injection","authors":"A. Derezińska","doi":"10.1109/PCEE.2004.32","DOIUrl":"https://doi.org/10.1109/PCEE.2004.32","url":null,"abstract":"This paper discusses estimation of dependability of a parallel FFT application. The application uses FFTW library. Fault susceptibility is assessed using software implemented fault injection. The fault injection campaign and the experiment results are presented. The response classes to injected faults are analyzed. The accuracy of evaluated data is verified experimentally.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125132777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Parallel program control based on hierarchically detected consistent global states 基于分层检测全局一致状态的并行程序控制
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.53
J. Borkowski
{"title":"Parallel program control based on hierarchically detected consistent global states","authors":"J. Borkowski","doi":"10.1109/PCEE.2004.53","DOIUrl":"https://doi.org/10.1109/PCEE.2004.53","url":null,"abstract":"Consistent global states (CGS) detection is a costly process. If CGS are constructed using real-time timestamps, then their hierarchical detection is possible. In a hierarchical detection scheme the load of a single central monitor is distributed among a number of monitors. We show, that hierarchical CGS detection has advantages over centralized detection: it allows for online monitoring of larger systems and for a more effective application control based on observed CGS. Hierarchical CGS detection can be coupled with a hierarchical application control scheme for better results. Further improvement is obtained if a timeout mechanism allows unterminated local states to be used for CGS construction. Relevant algorithms and simulation results are presented and discussed.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"58 9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122387033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
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