{"title":"Reconfigurable On-Chip SIMD Processor Architectures for Intelligent CMOS Camera Chips","authors":"D. Fey, L. Hoppe, A. Loos","doi":"10.1109/PCEE.2004.61","DOIUrl":"https://doi.org/10.1109/PCEE.2004.61","url":null,"abstract":"We present results of an investigation concerning the appropriateness of different parallel SIMD architectures based on reconfigurable approaches for an integration in an one-chip high speed smart CMOS camera. The processing elements (PEs) of the architecture combine parallel analogue optical signal detection and parallel digital signal processing to meet real-time requirements. However, the parallel architecture puts some constraints on the PE architecture. To achieve reasonable pixel resolutions and fill factors the PE area has to be as low as possible. Additionally a single PE must also offer sufficient functional flexibility. We show by a logic synthesis that reconfigurable architectures based on morphological operations are the best solution to fulfill these constraints. Furthermore we present simulation results of a first test chip which we designed as an OPTO-ASIC with a simple SIMD chip architecture.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123749750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Large-Scale Tolerance Analysis","authors":"D. Fimmel, Stefan Quitzk, W. Schwarz","doi":"10.1109/PCEE.2004.40","DOIUrl":"https://doi.org/10.1109/PCEE.2004.40","url":null,"abstract":"In this paper, we present an approach to the tolerance analysis of non-linear, time-invariant systems depending on statistical distributed parameters. The approach is based on an approximation of the performance function over the parameter domain which allows the determination of statistical properties of this function and provides appropriate information for the design adjustment. We show that parameter sensitivities and even higher order Taylor expansions of the performance function are not applicable in general, and propose an interpolation approach using power series. Finally, we give some remarks on the incorporation of our method in numerical simulation programs (e.g. spice), especially we discuss the reduction of computational efforts to outperform the Monte Carlo method, even for a larger number of parameters.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131973152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Program Graph Scheduling for SMP Clusters with Communication on-the-Fly Based on Extended DS Approach","authors":"L. Masko","doi":"10.1109/PCEE.2004.57","DOIUrl":"https://doi.org/10.1109/PCEE.2004.57","url":null,"abstract":"This paper deals with a problem of program graph scheduling for a parallel with dynamic processor switching and data transfers on the fly. The architecture of such system is based on a concept of SMP clusters implemented in network-on-chip (NoC) modules, which connect processors to shared memory modules. Processors can by dynamically switched between clusters at runtime, allowing dynamic distribution of computation and communication between processor clusters. The collective communication capabilities of an intra-cluster communication network allow using data reads on the fly for effective intra-cluster data transfers. It consists in parallel readings of data which are written or read to/from a memory module through an internal data exchange network by many processors in this cluster. The paper presents a two-level scheduling algorithm based on Extended Dominant Sequence. The higher-level part of the algorithm defines distribution of program graph nodes between NoC modules. The lower-level part determines the scheduling of the program graph for a given distribution of program nodes on processors and SMP clusters.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127106040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Seidel, G. Cichon, P. Robelly, M. Bronzel, G. Fettweis
{"title":"Hardware / Software Co-Design of a SIMD-DSP-Based DVB-T Receiver","authors":"H. Seidel, G. Cichon, P. Robelly, M. Bronzel, G. Fettweis","doi":"10.1109/PCEE.2004.35","DOIUrl":"https://doi.org/10.1109/PCEE.2004.35","url":null,"abstract":"The demand for increasing design complexity has to face decreasing design time and design cost issues. Traditional full custom design flows are not reasonable to cope with this challenges. We have developed a design exploration platform which provides access to main chip design parameters beginning from early design stages. With this platform, architecture and hardware/software partitioning failures are correctable with low change cost in a short time. Our designs are based on Synchronous Transfer Architecture SIMD DSP Cores with a tailored instruction set. Automatic Core Generation Tools speed up the design and verification process. In this paper we present our design exploration platform and a use case study for a DVB-T/H like OFDM-Receiver and Transmitter build with our design methodology.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132827175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}