{"title":"A Graphical Interface to a Parallel Solver: PSGE Description Through an Application","authors":"R. Bycul","doi":"10.1109/PCEE.2004.3","DOIUrl":"https://doi.org/10.1109/PCEE.2004.3","url":null,"abstract":"The paper describes a graphical interface to a parallel solver of systems of linear algebraic equations. The interface is used to simplify the process of preparing an environment for the parallel computations on Windows operating systems. The application has been run on a Windows 2000 based cluster of PCs. The solver part has been written in C, so that it was possible to implement and run it on two other Linux clusters for the results comparison.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"64 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130899406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Architecture and Functioning of Large-Scale Distributed Reconfigurable Computer Systems","authors":"V. Khoroshevsky","doi":"10.1109/PCEE.2004.14","DOIUrl":"https://doi.org/10.1109/PCEE.2004.14","url":null,"abstract":"Considered are architecture features and multicluster configuration of distributed reconfigurable computer systems. Studied are parallel multitasking regimes of functioning of large-scale computer systems. Described are games theory and stochastic programming approaches to obtain optimal functioning organizations of these systems.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129645070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Parallel Genetic Algorithms for Third Generation Mobile Network Planning","authors":"C. Maple, Liang Guo, Jie Zhang","doi":"10.1109/PCEE.2004.51","DOIUrl":"https://doi.org/10.1109/PCEE.2004.51","url":null,"abstract":"As Third Generation (3G) mobile networks start to be implemented, there is a need for effective network planning. However, deciding upon the optimum placement for the base stations of the networks is a complex task requiring vast computational resource. This paper discusses the conflicting objectives of base station planning and characterises a multi-objective optimisation problem. We present a genetic encoding of the third generation mobile network planning problem and parallel genetic algorithms to solve it.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"21 19","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114043824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Tool for Exploring the Large Scale Signal Processing Systems Specification","authors":"Sylvain Alliot, L. Nicolae, M. V. Veelen","doi":"10.1109/PCEE.2004.9","DOIUrl":"https://doi.org/10.1109/PCEE.2004.9","url":null,"abstract":"Large scale and/or distributed embedded system designs are hierarchies of platforms executing massively parallel processes. To design such systems one must follow multi level requirements to specification steps jointly in the application and architecture domains. These can not be anticipated and compared without assistance. We present here an exploration tool for such systems, which facilitates a novel approach for the evaluation of architectures based on the reuse of accumulated design knowledge. The tool bridges multiple domain entries: the topology, the mapping, the system constraints and the hardware components. A parameterized model of the system is built and later instantiated for different specification scenarios. Various user interfaces are provided to ease the different views on the specification and data entries. This information is passed on to an object oriented model for performance/cost analysis.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123401019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The Role of Parallel Computing at ABB Corporate Research Switzerland","authors":"A. Blaszczyk","doi":"10.1109/PCEE.2004.70","DOIUrl":"https://doi.org/10.1109/PCEE.2004.70","url":null,"abstract":"The paper presents a short summary of the invited talk to PARELEC 2004 conference in Dresden.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128637485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Scheduling Byte Code-Defined Data Dependence Graphs of Object Oriented Programs","authors":"E. Laskowski, R. Olejnik, B. Toursel, M. Tudruj","doi":"10.1109/PCEE.2004.63","DOIUrl":"https://doi.org/10.1109/PCEE.2004.63","url":null,"abstract":"This paper presents pre-optimization methods for distributed Java applications on Java Virtual Machines (JVMs), which reduce program execution time. On the basis of an analysis the byte code compiled for a program, an extended macro data flow graph is generated. To this graph clustering and scheduling algorithms are applied based on modified DSC heuristics. The algorithms define distribution of clusterized nodes and objects on JVMs, so as to reduce the total execution time of programs. The nodes of the macro data flow graph are distributed to different JVMs as dynamic threads of distributed objects by modification of the program byte code without modifications of Java virtual machines.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133763380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. Vonnahme, B. Griese, Mario Porrmann, U. Rückert
{"title":"Dynamic Reconfiguration of Real-Time Network Interfaces","authors":"E. Vonnahme, B. Griese, Mario Porrmann, U. Rückert","doi":"10.1109/PCEE.2004.29","DOIUrl":"https://doi.org/10.1109/PCEE.2004.29","url":null,"abstract":"The programmable resources of reconfigurable computing architectures are commonly used to support application specific processing. Dynamic reconfiguration enables hardware adaptation even during run-time. This paper concentrates on extending the application of dynamically reconfigurable logic to the area of network interface logic. The benefits and consequences of implementing even low-level networking functions in programmable hardware over fixed realizations are explained, and the possibilities arising from reconfigurable network interfaces are shown. Concerning reconfiguration of the network interface subsystem at run-time, maintaining connections, preventing packet loss, and guaranteeing response times during reconfiguration is crucial. Methods for dynamically replacing network interface hardware are described, and the current prototype is shown.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127602708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Co-Ordination of Parallel GRID Applications using Synchronizers","authors":"D. Kopanski, J. Borkowski, M. Tudruj","doi":"10.1109/PCEE.2004.18","DOIUrl":"https://doi.org/10.1109/PCEE.2004.18","url":null,"abstract":"Recently, the graphical parallel programming environment P-GRADE based on message passing has been extended by advanced synchronization and control mechanisms (synchronizers) based on predicates computed on consistent application global states (PS-GRADE). In the new P-GRADE Workflow system, the application workflow has been introduced to enable designing control flow between otherwise independent applications. In this paper, we propose that program execution control by synchronizers can be extended and used to coordinate parallel applications executed on GRID in the frame of a PS-GRADE tool. We introduce explicit inter-application, or GRID-level, synchronizers. They are connected to application level synchronizers, which are able to send state reports and receive control signals over GRID communication network. Open Grid Services Infrastructure, implemented using Globus toolkit, is proposed to be used for these purposes.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"13 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133699463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Performance Evaluation of Parallel MPEG-4 Video Coding Algorithms on Clusters of Workstations","authors":"A. Rodríguez, A. González, Manuel P. Malumbres","doi":"10.1109/PCEE.2004.55","DOIUrl":"https://doi.org/10.1109/PCEE.2004.55","url":null,"abstract":"During the last decade a lot of research and development efforts have been made to design competitive video codecs for several kinds of multimedia applications. Some video encoders like MPEG-4 and H.264 exhibit a very high computational cost, particularly in the case of high quality video sequences. Then, it is very difficult to find software solutions that efficiently code high-quality video in real-time or faster. We propose and evaluate several parallel implementations of the MPEG-4 standard encoder on clusters of workstations. We have performed extensive experiments showing that coding speed can be improved to more than double real-time requirements, being coding efficiency the same than the one in the sequential version.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116439665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Sauer, M. Gries, J. I. Gómez, S. Weber, K. Keutzer
{"title":"Developing a Flexible Interface for RapidIO, Hypertransport, and PCI-Express","authors":"C. Sauer, M. Gries, J. I. Gómez, S. Weber, K. Keutzer","doi":"10.1109/PCEE.2004.25","DOIUrl":"https://doi.org/10.1109/PCEE.2004.25","url":null,"abstract":"In communication centric application domains flexible interfaces are required to support the variety of recently emerged and still evolving high-speed serial interconnect standards. To develop such interfaces, typical application scenarios have to be identified, and common functionality and specific characteristics of the selected standards need to be analyzed. The results of this analysis can then guide the exploration of the design space. In this paper, we present a methodology which is tailored to the characteristics of serial interconnects. We use Click models for analysis and abstraction of the communication protocols and explore flexible interfaces within a cycle-accurate architecture development framework. Our results show the feasibility of implementing a flexible interface on a packet engine similar to those used in network processors. Based on our findings, we believe that flexible interfaces will form a new family of building blocks for future Systems-on-Chip.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122984713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}