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Matrix Multiplication Performance on Commodity Shared-Memory Multiprocessors 商用共享内存多处理器的矩阵乘法性能
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.43
G. Tsilikas, M. Fleury
{"title":"Matrix Multiplication Performance on Commodity Shared-Memory Multiprocessors","authors":"G. Tsilikas, M. Fleury","doi":"10.1109/PCEE.2004.43","DOIUrl":"https://doi.org/10.1109/PCEE.2004.43","url":null,"abstract":"Cache-oblivious algorithms for matrix multiplication are confirmed as an effective way of exploiting Intel architecture shared-memory multiprocessors. The performance also remains consistent across a wide range of matrix size. The Cilk programming environment remains an effective way of implementing this type of algorithm, but the need for portability and a compiler upgrade route mean that a portability library is a competitive alternative. The paper considers the interaction of matrix multiplication algorithms with the memory hierarchy, as well as multithreading across differing operating system variants and compilers.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131472189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Algorithm Partitioning including Optimized Data-Reuse for Processor Arrays 包括处理器阵列优化数据重用在内的算法划分
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.10
Sebastian Siegel, R. Merker
{"title":"Algorithm Partitioning including Optimized Data-Reuse for Processor Arrays","authors":"Sebastian Siegel, R. Merker","doi":"10.1109/PCEE.2004.10","DOIUrl":"https://doi.org/10.1109/PCEE.2004.10","url":null,"abstract":"This paper describes a method for algorithm partitioning through which affine indexed algorithms are transformed to Processor Arrays. Former design flows start with a spacetime transformation which we omit completely. Therefore, we are able to consider the constraints of a target architecture at the beginning of our design flow. We show our method for three different partitioning schemes and emphasize on the derivation of a schedule. The principle of an optimized data-reuse is introduced for our partitioning methodology. Under this aspect, we give a parameterized Processor Array for the 2D FIR filter algorithm.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"362 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127581677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Distributed Genetic Algorithm for Finding Fuzzy Rational Approximators 寻找模糊有理逼近器的分布式遗传算法
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.27
O. Brudaru, O. Buzatu
{"title":"Distributed Genetic Algorithm for Finding Fuzzy Rational Approximators","authors":"O. Brudaru, O. Buzatu","doi":"10.1109/PCEE.2004.27","DOIUrl":"https://doi.org/10.1109/PCEE.2004.27","url":null,"abstract":"This paper deals with the finding of a fuzzy rational function that best fits on a given set of input-output patterns of an unknown fuzzy dependency. In order to solve this problem a distributed genetic algorithm based on the island model is presented. Experimental investigations for evaluating the performance of the proposed distributed algorithm are also described.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"93 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133354156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Introducing Variable Sharing to Process Calculi 在过程演算中引入变量共享
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.39
S. Chrobot
{"title":"Introducing Variable Sharing to Process Calculi","authors":"S. Chrobot","doi":"10.1109/PCEE.2004.39","DOIUrl":"https://doi.org/10.1109/PCEE.2004.39","url":null,"abstract":"The π calculus models communication using synchronous channels which proved to be unrealistic in implementation. The join calculus eliminates the synchronous channels. It, however, still considers message-passing as the only communication form in distributed systems. We show that processes can share variables in local memories of system nodes, if they can travel among the nodes. We present a model which integrates passing and sharing communication in a common framework.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134339767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
The Parallel Computations for the Linear State Equations 线性状态方程的并行计算
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.69
A. Jordan, P. Myszkowski, Konrad Radzik
{"title":"The Parallel Computations for the Linear State Equations","authors":"A. Jordan, P. Myszkowski, Konrad Radzik","doi":"10.1109/PCEE.2004.69","DOIUrl":"https://doi.org/10.1109/PCEE.2004.69","url":null,"abstract":"In the presented article a multivariable linear state equation system ẋ = Ax + Bu, x(0) = x₀ was solved and a parallel version of the iterational algorithm was applied. The above method was used for the analysis of a system described by a huge number of state quations.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134256565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Hardware Accelerated Data Analysis 硬件加速数据分析
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.36
Marc Franzmeier, C. Pohl, Mario Porrmann, U. Rückert
{"title":"Hardware Accelerated Data Analysis","authors":"Marc Franzmeier, C. Pohl, Mario Porrmann, U. Rückert","doi":"10.1109/PCEE.2004.36","DOIUrl":"https://doi.org/10.1109/PCEE.2004.36","url":null,"abstract":"In this paper we present a massively parallel hardware accelerator for neural network based data mining applications. We use Self-Organizing Maps (SOM) for the analysis of very large datasets. One example is the analysis of semiconductor fabrication process data, which demands very high performance in order to achieve acceptable simulation times. Our system consists of Processing Elements (PEs) working completely in parallel on the task of SOM simulation. We will show the scalability of the system concerning precision and number of PEs, as well as the flexibility of the system regarding size and shape of the simulated maps. The possibility of emulating virtual maps (one PE emulates more than one neuron) enables the computation of maps with more neurons than PEs. Benchmarking results of our FPGA (Field Programmable Gate Array) based implementation of the system show the high performance of our accelerator.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124230255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Network application driven instruction set extensions for embedded processing clusters 嵌入式处理集群的网络应用驱动指令集扩展
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.45
M. Grünewald, Dinh Khoi Le, U. Kastens, Jörg-Christian Niemann, Mario Porrmann, U. Rückert, A. Slowik, Michael Thies
{"title":"Network application driven instruction set extensions for embedded processing clusters","authors":"M. Grünewald, Dinh Khoi Le, U. Kastens, Jörg-Christian Niemann, Mario Porrmann, U. Rückert, A. Slowik, Michael Thies","doi":"10.1109/PCEE.2004.45","DOIUrl":"https://doi.org/10.1109/PCEE.2004.45","url":null,"abstract":"This paper addresses the design automation of instruction set extensions for application-specific processors with emphasis on network processing. Within this domain, increasing performance demands and the ongoing development of network protocols both call for flexible and performance-optimized processors. Our approach represents a holistic methodology for the extension and optimization of a processor's instruction set. The starting point is a concise yet powerful processor abstraction, which is well suited to automatically generate the important parts of a compiler backend and cycle-accurate simulator so that domain-characteristic benchmarks can be analyzed for frequently occurring instruction pairs. These instruction pairs are promising candidates for the extension of the instruction set by means of super-instructions. Provided that a new super-instruction meets a given performance threshold, a fine-grained performance reevaluation of the adapted processor design can be conducted instantly. With respect to the chosen domain-characteristic benchmark, the tool-chain pinpoints important characteristics such as execution performance, energy consumption, or chip area of the extended design. Using this holistic design methodology, we are able to judge a refinement of the processor rapidly.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133813511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
A Design Environment for Processor-Like Reconfigurable Hardware 类处理器可重构硬件的设计环境
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.1
Tobias Oppold, Thomas Schweizer, T. Kuhn, W. Rosenstiel
{"title":"A Design Environment for Processor-Like Reconfigurable Hardware","authors":"Tobias Oppold, Thomas Schweizer, T. Kuhn, W. Rosenstiel","doi":"10.1109/PCEE.2004.1","DOIUrl":"https://doi.org/10.1109/PCEE.2004.1","url":null,"abstract":"There is a growing number of reconfigurable architectures that combine the advantages of a hardwired implementation (performance, power consumption) with the advantages of a software solution (flexibility, time to market). Today, there are devices on the market that can be dynamically reconfigured at run-time within one clock cycle. But the benefits of these architectures can only be utilized if applications can be mapped efficiently. In this paper we describe a design environment that takes into account the three aspects architecture, compiler, and applications, and we present the basic techniques that we use to realize the compiler.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130060368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Compiler Scheduling for STA-Processors sta处理器的编译器调度
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.20
G. Cichon, P. Robelly, H. Seidel, M. Bronzel, G. Fettweis
{"title":"Compiler Scheduling for STA-Processors","authors":"G. Cichon, P. Robelly, H. Seidel, M. Bronzel, G. Fettweis","doi":"10.1109/PCEE.2004.20","DOIUrl":"https://doi.org/10.1109/PCEE.2004.20","url":null,"abstract":"This paper presents an adaptation of the list scheduling algorithm to generate code for processors of the Synchronous Transfer Architecture (STA) by applying techniques known from RISC and TTA. The proposed scheduling approach is based on informed, deterministic algorithms that can be implemented run-time efficiently. Although the presented compiler prototype does not generate optimized code, it provides a proof-of-concept of the feasibility of the proposed compiler architecture.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"33 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125712668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Visualization of the Parallel Finite-Difference Time-Domain Method Computations Results 并行时域有限差分法计算结果的可视化
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.76
W. Walendziuk, A. Jordan, A. Skorek
{"title":"Visualization of the Parallel Finite-Difference Time-Domain Method Computations Results","authors":"W. Walendziuk, A. Jordan, A. Skorek","doi":"10.1109/PCEE.2004.76","DOIUrl":"https://doi.org/10.1109/PCEE.2004.76","url":null,"abstract":"This paper presents a visualization technique based on the OpenGL graphic standard of the parallel simulations of the electromagnetic field propagation. Such simulations are based on the parallel implementation of the Finite Differences Time Domain method. The algorithm is implemented in a homogeneous cluster system and uses the :stripe\" decomposition of the analyzed area.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133017270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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