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A New Memory Module for Memory Intensive Applications 一个新的内存模块为内存密集型应用
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.5
N. Tanabe, H. Nakajo, H. Hakozaki, M. Nakatake, Y. Dohi, H. Amano
{"title":"A New Memory Module for Memory Intensive Applications","authors":"N. Tanabe, H. Nakajo, H. Hakozaki, M. Nakatake, Y. Dohi, H. Amano","doi":"10.1109/PCEE.2004.5","DOIUrl":"https://doi.org/10.1109/PCEE.2004.5","url":null,"abstract":"Some applications with gather / scatter operations are difficult to accelerate. These operations cause inefficient cache use in each processor and fine grain global communications in parallel systems. There are several applications with such characteristics particularly in electrical engineering. For examples, circuit simulation and power flow simulation with LU decomposition for random sparse matrix has such characteristics. This paper presents how to make inexpensive personal supercomputers to solve these problems. In order to get the merit of commercial-off-the-shelf (COTS) continuously after the death of vector supercomputer vendors, it is designed without any modification on CPU, bridge chips on motherboard and memory chips. Only plugging a new memory module with vector load / store function and communication functions make an inexpensive home-use personal computer into a node similar to Earth simulator's one. Applications with unit striding or indexed accesses are going to be accelerated. How to accelerate NAS CG is shown as an example.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128556324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Fine-Grain Numerical Computations in Dynamic SMP Clusters with Communication on the Fly 动态通信SMP簇的细粒度数值计算
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.33
M. Tudruj, L. Masko
{"title":"Fine-Grain Numerical Computations in Dynamic SMP Clusters with Communication on the Fly","authors":"M. Tudruj, L. Masko","doi":"10.1109/PCEE.2004.33","DOIUrl":"https://doi.org/10.1109/PCEE.2004.33","url":null,"abstract":"This paper presents a new version of the dynamic SMP cluster -based architecture oriented towards networks on chip implementation technique. Smaller sub-networks with many dynamic SMP clusters and communication on the fly are connected by a central global network. Processors are provided with multi-ported data caches that enable parallel data transactions with memory modules, including parallel data pre-fetching and communication on the fly. Simulation experiments are described, based on a graph program representation and an automatic graph evaluator. They show efficiency of the proposed solution for very fine grain numerical problems.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126086471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Re-Configurable Parallel Stream Processor with Self-Assembling and Self-Restorable Micro-Architecture 具有自组装和自恢复微结构的可重构并行流处理器
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.60
L. Kirischian, Irina Terterian, P. Chun, V. Geurkov
{"title":"Re-Configurable Parallel Stream Processor with Self-Assembling and Self-Restorable Micro-Architecture","authors":"L. Kirischian, Irina Terterian, P. Chun, V. Geurkov","doi":"10.1109/PCEE.2004.60","DOIUrl":"https://doi.org/10.1109/PCEE.2004.60","url":null,"abstract":"In this paper we present a concept of the self-assembling micro-architectures of Application Specific Virtual Processors for data-stream processing. The procedure for micro-architecture assembling is developed for Xilinx \"Virtex\" FPGA devices. It is shown that proposed approach allows a minimization of system resources for multi-task data-stream workload and gives ability for self-restoration of processing micro-architectures when hardware fault occurs. This Paper presents a description of system level architecture of run-time re-configurable multi-stream parallel processor for video applications and results gained on the prototype.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126497187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Loop Scheduling for Multithreaded Processors 多线程处理器的循环调度
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.42
Georgios Dimitriou, C. Polychronopoulos
{"title":"Loop Scheduling for Multithreaded Processors","authors":"Georgios Dimitriou, C. Polychronopoulos","doi":"10.1109/PCEE.2004.42","DOIUrl":"https://doi.org/10.1109/PCEE.2004.42","url":null,"abstract":"The presence of multiple active threads on the same processor can mask latency by rapid context switching, but it can adversely affect performance due to competition for shared datapath resources. In this paper we present Macro Software Pipelining (MSWP), a loop scheduling technique for multithreaded processors, which is based on the loop distribution transformation for loop pipelining. MSWP constructs loop schedules by partitioning the loop body into tasks and assigning each task to a thread that executes all iterations for that particular task. MSWP is applied top-down on a hierarchical program representation, and utilizes thread-level speculation for maximal exploitation of parallelism. We tested MSWP on a multithreaded architectural model, Coral 2000, using synthetic and SPEC benchmarks. We obtained speedups of up to 30% with respect to highly optimized superblock-based schedules on loops with unpredictable branches, and a speedup of up to 25% on perl, a highly sequential SPEC95 integer benchmark.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125238124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Optimising MPI Applications for Heterogeneous Coupled Clusters with MetaMPICH 利用MetaMPICH优化异构耦合集群的MPI应用
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.48
Carsten Clauss, Martin Pöppe, T. Bemmerl
{"title":"Optimising MPI Applications for Heterogeneous Coupled Clusters with MetaMPICH","authors":"Carsten Clauss, Martin Pöppe, T. Bemmerl","doi":"10.1109/PCEE.2004.48","DOIUrl":"https://doi.org/10.1109/PCEE.2004.48","url":null,"abstract":"Cluster systems built mainly from commodity hardware components have become more and more usable for high performance computing tasks in the past few years. To increase the parallelism for applications, it is often desirable to combine those clusters to a higher lever, commonly called metacomputer. This class of high performance computing platforms can be understood as a cluster of clusters, where each cluster provides different processors, memory performance, cluster interconnect and external networking facilities. Our project called MetaMPICH provides a transparent MPI-1 implementation for those inhomogeneous cluster systems. While this feature of transparency makes porting existing MPI applications to metacomputers quite simple, the slowest network connection and the slowest processor will dominate the performance and scalability due to the lack of opacity. This paper describes our approaches to adapt iterative, grid based simulation algorithms to the structures of such heterogeneous coupled clusters.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124719199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
The Modified Speculative Method for the Transient States Analysis 暂态分析的修正推测法
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.68
J. Forenc, A. Jordan
{"title":"The Modified Speculative Method for the Transient States Analysis","authors":"J. Forenc, A. Jordan","doi":"10.1109/PCEE.2004.68","DOIUrl":"https://doi.org/10.1109/PCEE.2004.68","url":null,"abstract":"The speculative method is intended to conduct transient states analysis in electrical circuits in which the transient state is described by a system of ordinary differential equations (ODE), linear or non-linear. A general idea of this method is based on the decomposition of the time domain. Computations in subintervals of time are conducted in parallel with the use of one of wellknown sequential numerical methods of solving ODE systems. In the article the modified speculative method, then the analysis of a non-linear model of a DC-motor supplied by a solar generator, as an example of the application of this method, will be presented. The computations were carried out with the use of the cluster of 5 workstations based on Intel Xeon 2.66 GHz processor.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132000977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Employing Compilers for Determining Architectural Features of Application-Specific DSPs 使用编译器来确定特定应用dsp的体系结构特征
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.31
Jie Guo, M. Hosemann, G. Fettweis
{"title":"Employing Compilers for Determining Architectural Features of Application-Specific DSPs","authors":"Jie Guo, M. Hosemann, G. Fettweis","doi":"10.1109/PCEE.2004.31","DOIUrl":"https://doi.org/10.1109/PCEE.2004.31","url":null,"abstract":"In order to achieve high performance and low hardware overhead over application specific integrated circuits (ASICs), application-specific DSPs (AS-DSPs) are more and more widely used. However, designing them is still a tedious, time-consuming and error-prone task since each application has to be analyzed thoroughly, which is usually done by hand. Recently, we proposed a platform approach to design data paths for AS-DSPs. In this paper we are introducing a compiler-based methodology to speed-up and simplify the customization of the data path platform. Based on the SUIF compiler framework by Stanford University, we implemented analysis passes to determine the kind and useful number of functional units, the potential degree of parallelism, and the required connectivity between functional units.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114943087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Program Scheduling in Look-Ahead Reconfigurable Parallel Systems with Multiple Communication Resources 具有多通信资源的预见性可重构并行系统的程序调度
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.58
E. Laskowski
{"title":"Program Scheduling in Look-Ahead Reconfigurable Parallel Systems with Multiple Communication Resources","authors":"E. Laskowski","doi":"10.1109/PCEE.2004.58","DOIUrl":"https://doi.org/10.1109/PCEE.2004.58","url":null,"abstract":"The paper presents new graph structuring algorithms for look-ahead reconfigurable multi-processor systems. This architectural model is based on preparation of inter-processor link connections in advance in redundant communication resources (i.e. crossbar switches) in parallel with program execution, which enables elimination of connection reconfiguration time overheads. Application programs are partitioned into sections, which are executed using connections prepared in redundant communication resources. Parallel program structuring for execution in such systems incorporates task scheduling and graph partitioning problems. Presented algorithms apply two-phase approach, in which program task scheduling is solved by modified ETF heuristics and, in a second phase, a new iterative clustering heuristics is used for graph partitioning. The experimental results are presented, which compare performance of several graph partitioning heuristics for such environment.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132127427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Moldable Task Scheduling in Dynamic SMP Clusters with Communication on the Fly 动态SMP集群中动态通信的可塑任务调度
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.44
L. Masko, G. Mounié, D. Trystram, M. Tudruj
{"title":"Moldable Task Scheduling in Dynamic SMP Clusters with Communication on the Fly","authors":"L. Masko, G. Mounié, D. Trystram, M. Tudruj","doi":"10.1109/PCEE.2004.44","DOIUrl":"https://doi.org/10.1109/PCEE.2004.44","url":null,"abstract":"The paper concerns task graph scheduling in parallel programs using the concept of moldable computational tasks for a parallel architecture based on dynamic SMP processor clusters with data transmissions on the fly. The presented algorithm for scheduling parallel program graphs decomposes an initial program graph to sub-graphs, which fulfill the definition of a moldable task. So identified moldable tasks are then scheduled using an algorithm with warranted schedule length.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124784242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Using ModelSim, Matlab/Simulink and NS for Simulation of Distributed Systems 利用ModelSim、Matlab/Simulink和NS对分布式系统进行仿真
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.74
U. Hatnik, S. Altmann
{"title":"Using ModelSim, Matlab/Simulink and NS for Simulation of Distributed Systems","authors":"U. Hatnik, S. Altmann","doi":"10.1109/PCEE.2004.74","DOIUrl":"https://doi.org/10.1109/PCEE.2004.74","url":null,"abstract":"In this paper a flexible concept for simulator coupling is introduced which permits the whole system simulation of distributed systems, e.g. of complex communication systems. In our approach we use different languages (Matlab-Code, VHDL, oTcl, C/C++) and combine the specialized simulators Matlab/Simulink, ModelSim and the network simulator NS-2. Matlab/Simulink and ModelSim are shipped with a powerful foreign language interface and for NS-2 we developed a solution for including user written functions. The simulators are extended with a special coupling component implemented in C/C++. The simulator coupling bases on TCP/IP sockets, so that the simulation of the model parts can run on different host computers using different platforms.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116019248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 51
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