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Parallel Computing in Electrical Engineering, 2004. International Conference on最新文献

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A Modified Vertex Method for Parallelization of Arbitrary Nested Loops 任意嵌套循环并行化的改进顶点法
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.4
W. Bielecki, R. Kocisz
{"title":"A Modified Vertex Method for Parallelization of Arbitrary Nested Loops","authors":"W. Bielecki, R. Kocisz","doi":"10.1109/PCEE.2004.4","DOIUrl":"https://doi.org/10.1109/PCEE.2004.4","url":null,"abstract":"A technique, permitting us to linearize constraints formed to find affine schedules for arbitrary nested loops, is presented. The main advantage of this technique is that it does not require finding the polytope vertices and results in the fewer number of inequalities and equalities than that yielded with the vertex technique. Affine schedules found are valid for the arbitrary positive lower and upper loop bounds. Experiments with the Livermore loops are discussed. The restriction of the technique and tasks for future research are discussed.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"338 2‐3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132419247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Dynamically Reconfigurable Hardware for Object-Oriented Processing 面向对象处理的动态可重构硬件
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.30
Andreas Kühn, S. Huss
{"title":"Dynamically Reconfigurable Hardware for Object-Oriented Processing","authors":"Andreas Kühn, S. Huss","doi":"10.1109/PCEE.2004.30","DOIUrl":"https://doi.org/10.1109/PCEE.2004.30","url":null,"abstract":"The focus of this paper is to establish a link of dynamic structures as found in software-based systems function descriptions to hardware implementations. Specific properties of object-oriented software methodologies and partially reconfigurable FPGAs are first analyzed. Then, both a reconfigurable processing unit and an approach how to map object classes to such execution units are elaborated. The feasibility of the proposed mapping method is demonstrated for some application examples.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122901369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Digital Electromagnetic Model of the Power System: Parallel Implementation for Multicomputers 电力系统的数字电磁模型:多机并行实现
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.26
V. Malyshkin, I. Naumkin, N. Malyshkin, V. Korneev, M. Ostapkevich
{"title":"Digital Electromagnetic Model of the Power System: Parallel Implementation for Multicomputers","authors":"V. Malyshkin, I. Naumkin, N. Malyshkin, V. Korneev, M. Ostapkevich","doi":"10.1109/PCEE.2004.26","DOIUrl":"https://doi.org/10.1109/PCEE.2004.26","url":null,"abstract":"A digital electromagnetic model of electric power system is suggested. The parallel and the sequential algorithms to solve the equation set are described. Implementation of the parallel algorithm on k processors provides more then k times speedup.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"26 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120989167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Implementation of the Massively Parallel Model GCA 大规模并行模型GCA的实现
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.37
R. Hoffmann, W. Heenes, M. Halbach
{"title":"Implementation of the Massively Parallel Model GCA","authors":"R. Hoffmann, W. Heenes, M. Halbach","doi":"10.1109/PCEE.2004.37","DOIUrl":"https://doi.org/10.1109/PCEE.2004.37","url":null,"abstract":"The GCA (Global Cellular Automata) model is a very interesting model which can be used to implement all kind of parallel problems. The GCA model consists of a field of cells as in the Cellular Automata model. Each cell has links to a set of remote cells which can be dynamically changed from generation to generation. A cell reads the remote neighbour's states and then changes its own state according to a local rule. The model is massively parallel because all cells can change their states independently in parallel. We have investigated how the GCA model can be implemented efficiently in hardware using a FPGA prototyping platform. We have implemented a fully parallel architecture where all cells really operate in parallel and another architecture where the cells are stored in memories in order to handle a large number of cells. We are showing that in the fully parallel architecture a speed-up of more than 3000 compared to a software implementation on a PC is realistic on a modern FPGA platform. In the partially parallel architecture based on memories the speed-up will be lower but the number of cells is only restricted by the capacity of the memories.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"39 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120990505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A Novel Architecture of Arithmetic Coder in JPEG2000 Based on Parallel Symbol Encoding 一种基于并行符号编码的JPEG2000算法编码器结构
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.6
G. Pastuszak
{"title":"A Novel Architecture of Arithmetic Coder in JPEG2000 Based on Parallel Symbol Encoding","authors":"G. Pastuszak","doi":"10.1109/PCEE.2004.6","DOIUrl":"https://doi.org/10.1109/PCEE.2004.6","url":null,"abstract":"This paper presents a high-performance architecture of the context adaptive binary arithmetic coder (CABAC) for the embedded block-coding algorithm in JPEG 2000. The architecture has been developed in two variants to code two or three context-symbol pairs per clock cycle. The inverse multiple branch selection (IMBS) method is proposed to minimize critical paths, which originate from causally dependent operations. The designs have been implemented in VHDL and synthesized for FPGA devices. Simulation results show that the two- and three-symbol engines can process about 22 million samples at 77 and 53 MHz working frequency, respectively.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121081145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Demonstrator: Reuse Automation for Reconfigurable System-on-Chip Design within a DVB Environment 演示:DVB环境下可重构片上系统设计的重用自动化
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.24
Jörg Schneider, Vincent Kotzsch, Steffen Rülke
{"title":"Demonstrator: Reuse Automation for Reconfigurable System-on-Chip Design within a DVB Environment","authors":"Jörg Schneider, Vincent Kotzsch, Steffen Rülke","doi":"10.1109/PCEE.2004.24","DOIUrl":"https://doi.org/10.1109/PCEE.2004.24","url":null,"abstract":"With this demonstrator we present a new reuse based design methodology for the development of FEC (Forward Error Correction) applications for reconfigurable SoC (System-on-Chip) architectures. This approach enables the reuse of well tested and optimized RS- (Reed-Solomon) codec modules consisting of both HW and SW. Specific RS codec modules can be generated by generator tools. In order to automate the reuse process for dynamically reconfigurable SoCs, the generator tool supports the generation of design modules, interfaces and design flows. We examined our design methodology and RS codec modules within the SFB-358 demonstrator.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115873121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Parallel Tabu Search Method Approach for Very Difficult Permutation Scheduling Problems 极难置换调度问题的并行禁忌搜索方法
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.54
W. Bożejko, M. Wodecki
{"title":"Parallel Tabu Search Method Approach for Very Difficult Permutation Scheduling Problems","authors":"W. Bożejko, M. Wodecki","doi":"10.1109/PCEE.2004.54","DOIUrl":"https://doi.org/10.1109/PCEE.2004.54","url":null,"abstract":"There are very many issues, where scheduling can be applied, in computer systems (single and multiprocessors) as well as in production systems. Scheduling problems belongs in most cases to NP-hard class. For most of classical scheduling problems, published in last 10 years (for example benchmarks of Taillard [Benchmarks for basic scheduling problems] for the flow shop problem), there are still no optimal solutions. In this paper we propose very effective method of construct parallel algorithms based on tabu search metaheuristic. We apply block properties, which enable parallel algorithm to distribute calculations and reduce communication between processors. Algorithms are implemented in Ada95 and MPI.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130860235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Using Switched Ethernet for Hard Real-Time Communication 使用交换以太网实现硬实时通信
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.75
Jork Löser, Hermann Härtig
{"title":"Using Switched Ethernet for Hard Real-Time Communication","authors":"Jork Löser, Hermann Härtig","doi":"10.1109/PCEE.2004.75","DOIUrl":"https://doi.org/10.1109/PCEE.2004.75","url":null,"abstract":"Previous results on traffic shaping on Switched Ethernet technology demonstrate its practicability and effectiveness for hard real-time communication [Low-latency hard real-time communication over switched ethernet]. The application-to-application delays on a 5-node network were reported to be less than a millisecond with both Fast Ethernet and Gigabit Ethernet technology with a link utilization of 93% and 49%. In this paper we describe directions of research to extend this work, targeting performance bottlenecks we identified in the current design. We present ideas on offloading the traffic shaping process and the receive process into the firmware of a network interface card (NIC) and we refine the one-shot reservation protocol for best-effort traffic.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130982414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
Hardware/software co-design of a SIMD-DSP-based DVB-T receiver 基于simd - dsp的DVB-T接收机的软硬件协同设计
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PARELEC.2004.35
H. Seidel, G. Cichon, P. Robelly, M. Bronzel, G. Fettweis
{"title":"Hardware/software co-design of a SIMD-DSP-based DVB-T receiver","authors":"H. Seidel, G. Cichon, P. Robelly, M. Bronzel, G. Fettweis","doi":"10.1109/PARELEC.2004.35","DOIUrl":"https://doi.org/10.1109/PARELEC.2004.35","url":null,"abstract":"The demand for increasing design complexity has to face decreasing design time and design cost issues. Traditional full custom design flows are not reasonable to cope with these challenges. We have developed a design exploration platform, which provides access to main chip design parameters beginning from early design stages. With this platform, architecture and hardware/software partitioning failures are correctable with low change cost in a short time. Our designs are based on synchronous transfer architecture SIMD DSP cores with a tailored instruction set. Automatic core generation tools speed up the design and verification process. In this paper we present our design exploration platform and a use case study for a DVB-T/H like OFDM-receiver and transmitter build with our design methodology.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123444566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Tuning of Parallel ROI Matching Algorithms 并行ROI匹配算法的调整
Parallel Computing in Electrical Engineering, 2004. International Conference on Pub Date : 2004-09-07 DOI: 10.1109/PCEE.2004.73
J. Saif, H. Krawczyk
{"title":"Tuning of Parallel ROI Matching Algorithms","authors":"J. Saif, H. Krawczyk","doi":"10.1109/PCEE.2004.73","DOIUrl":"https://doi.org/10.1109/PCEE.2004.73","url":null,"abstract":"The prallel environmnets : PVM and .NET are considered and their suitability for image matching algorithms (IMA) are analysed. The class of IMA consisted of water filling and simulated annealing strategies are taken into account. Basic control parametrs of IMA are determined to achieve the highest similarity degree of compared images.","PeriodicalId":338403,"journal":{"name":"Parallel Computing in Electrical Engineering, 2004. International Conference on","volume":"19 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123561597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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