Proceedings Design, Automation and Test in Europe Conference and Exhibition最新文献_第3页

From synchronous to asynchronous: an automatic approach 从同步到异步:一种自动方法

Proceedings Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2004-02-16 DOI: 10.1109/DATE.2004.1269092

J. Cortadella, A. Kondratyev, L. Lavagno, K. Lwin, C. Sotiriou

引用次数: 19

MATLAB/SIMULINK-based high-level synthesis of discrete-time and continuous-time /spl Sigma//spl Delta/ modulators 基于MATLAB/ simulink的离散时间和连续时间/spl Sigma//spl Delta/调制器的高级合成

Proceedings Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2004-02-16 DOI: 10.1109/DATE.2004.1269222

J. Ruiz-Amaya, J. M. de la Rosa, F. Medeiro, F. Fernández, R. del Río, B. Pérez-Verdú, Á. Rodríguez-Vázquez

引用次数: 16

A low cost individual-well adaptive body bias (IWABB) scheme for leakage power reduction and performance enhancement in the presence of intra-die variations 一种低成本的单井自适应体偏置(IWABB)方案，用于在存在模内变化的情况下降低泄漏功率并提高性能

Proceedings Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2004-02-16 DOI: 10.1109/DATE.2004.1268855

Tom W. Chen, Justin Gregg

引用次数: 16

Simultaneous state, Vt and Tox assignment for total standby power minimization 同时状态，Vt和Tox分配以使总备用功率最小化

Proceedings Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2004-02-16 DOI: 10.1109/DATE.2004.1268894

Dongwook Lee, H. Singh, D. Blaauw, D. Sylvester

{"title":"Simultaneous state, Vt and Tox assignment for total standby power minimization","authors":"Dongwook Lee, H. Singh, D. Blaauw, D. Sylvester","doi":"10.1109/DATE.2004.1268894","DOIUrl":"https://doi.org/10.1109/DATE.2004.1268894","url":null,"abstract":"Standby leakage current minimization is a pressing concern for mobile applications that rely on standby modes to extend battery life. Also, gate oxide leakage current (I/sub gate/) has become comparable to subthreshold leakage (I/sub sub/) in 90 nm technologies. In this paper, we propose a new method that uses a combined approach of sleep-state, threshold voltage (V/sub t/ and gate oxide thickness (T/sub ox/) assignments in a dual-V/sub t/ and dual-T/sub ox/ process to minimize both I/sub sub/ and I/sub gate/. Using this method, total leakage current can be dramatically reduced since in a known state in standby mode, only certain transistors are responsible for leakage current and need to be considered for high-V/sub t/ or thick-T/sub ox/ assignment. We formulate the optimization problem for simultaneous state, V/sub t/ and T/sub ox/ assignments under delay constraints and propose two practical heuristics. We implemented and tested the proposed methods on a set of synthesized benchmark circuits. Results show an average leakage current reduction of 5a-6X and 2-3X compared to previous approaches that only use state or state+V/sub t/ assignment, respectively, with small delay penalties.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116523619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 27

Multi-processor SoC design methodology using a concept of two-layer hardware-dependent software

Proceedings Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2004-02-16 DOI: 10.1109/DATE.2004.1269098

S. Yoo, M. Youssef, A. Bouchhima, A. Jerraya, M. Diaz-Nava

引用次数: 14

Low static-power frequent-value data caches 低静态功率频率值数据缓存

Proceedings Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2004-02-16 DOI: 10.1109/DATE.2004.1268851

Chuanjun Zhang, Jun Yang, F. Vahid

{"title":"Low static-power frequent-value data caches","authors":"Chuanjun Zhang, Jun Yang, F. Vahid","doi":"10.1109/DATE.2004.1268851","DOIUrl":"https://doi.org/10.1109/DATE.2004.1268851","url":null,"abstract":"Static energy dissipation in cache memories will constitute an increasingly larger portion of total microprocessor energy dissipation due to nanoscale technology characteristics and the large size of on-chip caches. We propose to reduce the static energy dissipation of an on-chip data cache by taking advantage of the frequent values (FV) that widely exist in a data cache memory. The original FV-based low-power cache design aimed at only reducing dynamic power, at the cost of a 5% slowdown. We propose a better design that reduces both static and dynamic cache power, and that uses a circuit design that eliminates performance overhead. A designer can utilize our architecture by simulating an application and then synthesizing the FVs into an application-specific cache design when values will not change, or by simulating and then writing to an FV-cache with configuration registers when values could change. Furthermore, we describe hardware that can dynamically determine FVs and write to the configuration registers completely transparently. Experiments on 11 Spec 2000 benchmarks show that, in addition to the dynamic power savings, 33% static energy savings for data caches can be achieved.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122427259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 22

Synthesis of partitioned shared memory architectures for energy-sufficient multi-processor SoC 能量充足的多处理器SoC分区共享内存架构的综合

Proceedings Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2004-02-16 DOI: 10.1109/DATE.2004.1268937

Kimish Patel, E. Macii, M. Poncino

引用次数: 12

Breaking instance-independent symmetries in exact graph coloring 精确图着色中实例无关对称性的破缺

Proceedings Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2004-02-16 DOI: 10.1613/jair.1637

Arathi Ramani, F. Aloul, I. Markov, K. Sakallah

引用次数: 54

Workload characterization model for tasks with variable execution demand 具有可变执行需求的任务的工作负载表征模型

Proceedings Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2004-02-16 DOI: 10.1109/DATE.2004.1269030

A. Maxiaguine, S. Künzli, L. Thiele

引用次数: 83

Circularscan: a scan architecture for test cost reduction Circularscan:用于降低测试成本的扫描架构

Proceedings Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2004-02-16 DOI: 10.1109/DATE.2004.1269073

B. Arslan, A. Orailoglu

引用次数: 55