Proceedings Design, Automation and Test in Europe Conference and Exhibition最新文献_第4页

Impact of data transformations on memory bank locality 数据转换对内存库局部性的影响

Proceedings Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2004-02-16 DOI: 10.1109/DATE.2004.1268896

M. Kandemir

引用次数: 10

Impact of test point insertion on silicon area and timing during layout 测试点插入对布局时硅面积和时间的影响

Proceedings Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2004-02-16 DOI: 10.1109/DATE.2004.1268981

H. Vranken, Ferry Syafei Sapei, H. Wunderlich

引用次数: 20

A game theoretic approach to low energy wireless video streaming 低能量无线视频流的博弈论方法

Proceedings Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2004-02-16 DOI: 10.1109/DATE.2004.1268935

A. Iranli, Kihwan Choi, Massoud Pedram

引用次数: 0

Aspects of formal and graphical design of a bus system 公交系统的形式设计和图形设计

Proceedings Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2004-02-16 DOI: 10.1109/DATE.2004.1268879

T. Seceleanu, T. Westerlund

引用次数: 3

Timing correction and optimization with adaptive delay sequential elements 自适应延迟序列元件的时序校正与优化

Proceedings Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2004-02-16 DOI: 10.1109/DATE.2004.1269114

K. Rahimi, S. Bridges, C. Diorio

引用次数: 2

Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip 在芯片上的nostrum网络内的暂时不连接的网络中使用环形容器保证带宽

Proceedings Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2004-02-16 DOI: 10.1109/DATE.2004.1269001

Mikael Millberg, E. Nilsson, R. Thid, A. Jantsch

{"title":"Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip","authors":"Mikael Millberg, E. Nilsson, R. Thid, A. Jantsch","doi":"10.1109/DATE.2004.1269001","DOIUrl":"https://doi.org/10.1109/DATE.2004.1269001","url":null,"abstract":"In today's emerging network-on-chips, there is a need for different traffic classes with different quality-of-service guarantees. Within our NoC architecture nostrum, we have implemented a service of guaranteed bandwidth (GB), and latency, in addition to the already existing service of best-effort (BE) packet delivery. The guaranteed bandwidth is accessed via virtual circuits (VC). The VCs are implemented using a combination of two concepts that we call 'Looped Containers' and 'Temporally Disjoint Networks'. The looped containers are used to guarantee access to the network-independently of the current network load without dropping packets; and the TDNs are used in order to achieve several VCs, plus ordinary BE traffic, in the network. The TDNs are a consequence of the deflective routing policy used, and gives rise to an explicit time-division-multiplexing within the network. To prove our concept an HDL implementation has been synthesised and simulated. The cost in terms of additional hardware needed, as well as additional bandwidth is very low-less than 2 percent in both cases! Simulations showed that ordinary BE traffic is practically unaffected by the VCs.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126218891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 429

Polynomial abstraction for verification of sequentially implemented combinational circuits 验证顺序实现组合电路的多项式抽象

Proceedings Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2004-02-16 DOI: 10.1109/DATE.2004.1268933

Tarvo Raudvere, A. Singh, I. Sander, A. Jantsch

引用次数: 1

A fast word-level statistical estimator of intra-bus crosstalk 总线内串扰的快速字级统计估计

Proceedings Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2004-02-16 DOI: 10.1109/DATE.2004.1269041

Suvodeep Gupta, S. Katkoori

{"title":"A fast word-level statistical estimator of intra-bus crosstalk","authors":"Suvodeep Gupta, S. Katkoori","doi":"10.1109/DATE.2004.1269041","DOIUrl":"https://doi.org/10.1109/DATE.2004.1269041","url":null,"abstract":"Given word-level statistics, namely mean, standard deviation, and lag-one temporal correlation of input data, we estimate the bit-level crosstalk probability on a system bus using a non-enumerative statistical approach. We introduce a sampling technique for fast evaluation of integrals during the estimation process. We had proposed two techniques previously - (a) a stream-based estimator that counts crosstalk events on a bus; and (b) a statistical enumeration technique that enumerates crosstalk-producing values on a bus and computes their occurrence probability. Both these techniques suffer from exponential time complexity with respect to the bus-width. In this work, we propose a statistical non-enumerative technique that has linear time complexity with respect to the bus-width. We achieve the linear complexity by resorting to: (1) manipulating the data stream to make the crosstalk-producing values contiguous and (2) sampling the distribution function and storing it as a lookup table. Experimental results for data streams from different data environments are presented, compared against the stream-based approach. Average errors of less than 12% are obtained for bus-widths ranging from 8b to 32b.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128202231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Re-configurable bus encoding scheme for reducing power consumption of the cross coupling capacitance for deep sub-micron instruction bus 降低深亚微米指令总线交叉耦合电容功耗的可重构总线编码方案

Proceedings Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2004-02-16 DOI: 10.1109/DATE.2004.1268838

S. Wong, C. Tsui

{"title":"Re-configurable bus encoding scheme for reducing power consumption of the cross coupling capacitance for deep sub-micron instruction bus","authors":"S. Wong, C. Tsui","doi":"10.1109/DATE.2004.1268838","DOIUrl":"https://doi.org/10.1109/DATE.2004.1268838","url":null,"abstract":"In very deep sub-micron designs, cross coupling capacitances become the dominant factor of the total bus loading and have a significant impact on the power consumption. In this paper, we propose two reconfigurable bus encoding schemes, which are based on the correlation among the bit lines, to reduce the power consumption at the cross coupling capacitances of the instruction buses. The instruction is encoded by flipping and reordering the bit lines during compilation time to reduce the total switching capacitances. A crossbar is used to map back the data to the original instruction code before sending to the instruction decoder. The reordering can be re-configured during run-time by using different configurations in the crossbar. We propose two types of re-configuration, static and dynamic. Static coding uses a fix flipping and re-configuring pattern after the corresponding program is compiled. Dynamic coding allows different re-configuring patterns during program execution. Experimental results show that by using the proposed schemes, significant energy reduction, 17-23%, can be achieved. Comparisons with existing bit lines reordering encoding scheme have also been made and on average more than 15% reduction can be obtained using our method.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130834465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

Mapping multi-million gate SoCs on FPGAs: industrial methodology and experience 在fpga上映射数百万门soc:工业方法和经验

Proceedings Design, Automation and Test in Europe Conference and Exhibition Pub Date : 2004-02-16 DOI: 10.1109/DATE.2004.1269065

H. Krupnova

引用次数: 33