2015 Fifth International Conference on Communication Systems and Network Technologies最新文献_第2页

Design and Research the Control Technology of Blade Life Hydraulic Test Bench Based on an Accumulator 基于蓄能器的叶片寿命液压试验台控制技术设计与研究

2015 Fifth International Conference on Communication Systems and Network Technologies Pub Date : 2015-10-01 DOI: 10.1109/CSNT.2015.213

Zhang Yakui, Ruixiang Zhou, Zhang Jin, Lvlong He

{"title":"Design and Research the Control Technology of Blade Life Hydraulic Test Bench Based on an Accumulator","authors":"Zhang Yakui, Ruixiang Zhou, Zhang Jin, Lvlong He","doi":"10.1109/CSNT.2015.213","DOIUrl":"https://doi.org/10.1109/CSNT.2015.213","url":null,"abstract":"In order to study high and low cycle fatigue experiment bench control technology of a certain type of aircraft engine fan blade, we can reach the purpose of reducing the pressure pulsation of system and improving the stability of the test loading force. By means of simulation, we first designed the experiment bench model of high-low cycle fatigue based on MATLAB/Sim Hydraulics. Then on the basis of the system model, we completed the simulation according to the following steps: changing the position and loading ways of the accumulator in the hydraulic test bench, matching the system with different parameters. From the study can we find that the simulation of high-low cycle fatigue test rig has reached the expected purpose. At the same time, we got the effective parameter selection. In the process of simulation, we also found that the introduction of the accumulator can give great buffer effect to pressure pulsation which produced by the sudden closing of valves. At the mean time, the accumulator can bring more stable loading force. In conclusion, this study can provide necessary guidance to the design and production of experiment bench, so that we can get better experiment results.","PeriodicalId":334733,"journal":{"name":"2015 Fifth International Conference on Communication Systems and Network Technologies","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121556564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

An Overview of Behavioral Analaysis Using Social Web Site Data 使用社交网站数据的行为分析概述

2015 Fifth International Conference on Communication Systems and Network Technologies Pub Date : 2015-04-04 DOI: 10.1109/CSNT.2015.67

S. S. Husain, S. Dhopte

引用次数: 1

A Hybrid Approach for Network Intrusion Detection 一种网络入侵检测的混合方法

2015 Fifth International Conference on Communication Systems and Network Technologies Pub Date : 2015-04-04 DOI: 10.1109/CSNT.2015.76

G. P. Rout, S. Mohanty

引用次数: 25

Effect of Selfish Behavior on Network Performance in VANET 自利行为对网络绩效的影响

2015 Fifth International Conference on Communication Systems and Network Technologies Pub Date : 2015-04-04 DOI: 10.1109/CSNT.2015.63

Pratibha Pandey

引用次数: 2

HDL Design for 20 Tbps Multichannel 64:1 LVDS Data Serializer & De-serializer ASIC Array Card Design 20tbps多通道64:1 LVDS数据串行器的HDL设计反序列化ASIC阵列卡设计

2015 Fifth International Conference on Communication Systems and Network Technologies Pub Date : 2015-04-04 DOI: 10.1109/CSNT.2015.108

P. Sastry, D. Rao

引用次数: 1

A Comparison Study on Route Stability of On-Demand Routing Protocols in CRAHNs crahn中按需路由协议路由稳定性的比较研究

2015 Fifth International Conference on Communication Systems and Network Technologies Pub Date : 2015-04-04 DOI: 10.1109/CSNT.2015.218

A. Dhawan, Sandhya Aneja, Shikha Jain, C. K. Jha

引用次数: 0

Transliteration of Digital Gujarati Text Into Printable Braille 数字古吉拉特文本转写为可打印的盲文

2015 Fifth International Conference on Communication Systems and Network Technologies Pub Date : 2015-04-04 DOI: 10.1109/CSNT.2015.82

Nikisha B. Jariwala, Bankim Patel

引用次数: 6

Design and Implementation of Low Bit Error Rate of LDPC Decoder 低误码率LDPC解码器的设计与实现

2015 Fifth International Conference on Communication Systems and Network Technologies Pub Date : 2015-04-04 DOI: 10.1109/CSNT.2015.161

Ashlesha P. Kshirsagar, Sandeep Kakde, M. Chawhan, Y. Suryawanshi

引用次数: 1

Design and Implementation of Floating Point Divide-Add Fused Architecture 浮点除法加融合体系结构的设计与实现

2015 Fifth International Conference on Communication Systems and Network Technologies Pub Date : 2015-04-04 DOI: 10.1109/CSNT.2015.179

Kuldeep Pande, A. Parkhi, S. Jaykar, A. Peshattiwar

{"title":"Design and Implementation of Floating Point Divide-Add Fused Architecture","authors":"Kuldeep Pande, A. Parkhi, S. Jaykar, A. Peshattiwar","doi":"10.1109/CSNT.2015.179","DOIUrl":"https://doi.org/10.1109/CSNT.2015.179","url":null,"abstract":"Many Floating Point operations have been acknowledged to be useful for many real time graphic and multimedia application as well as DSP processors. Many Digital Signal Processing algorithms use Floating point arithmetic, which requires millions of calculations per second to be performed. For such stringent requirements, design of fast, precise and efficient circuits is the goal. This brief presents a dedicated unit for the combined operation of floating-point (FP) division followed byaddition/subtraction -- the divide -- add fused (DAF). The goal of this unit is to increase the performance and the accuracy of applications where this combined operation is frequent, such as the interval Newton's method or the polynomial approximation. The proposed DAF unit presents a similar architecture to the FP multiply accumulateunits. The main difference is represented by the divider, which is implemented using digit-recurrence algorithms. An important design trade off regarding DAFis represented by the number of required quotient bits. We present the impact of the adopted number of quotient bits on accuracy, cost, and performance. We show that the proposed implementations have better accuracy with respect to the solution based on two distinct units: an FP divider and an FP adder. This implementation is suitable for lower latency, accuracy and best cost-performance trade off. The proposed unit is synthesized for4vfx60ff672-12 Xilinx Spartan-6 FPGA.","PeriodicalId":334733,"journal":{"name":"2015 Fifth International Conference on Communication Systems and Network Technologies","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114465322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Analysis of the Hand Motion Trajectories for Recognition of Air-Drawn Symbols 手绘符号识别的手部运动轨迹分析

2015 Fifth International Conference on Communication Systems and Network Technologies Pub Date : 2015-04-04 DOI: 10.1109/CSNT.2015.95

N. Ayachi, Piyush Kejriwal, Lalit Kane, P. Khanna

引用次数: 6