2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)最新文献

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Wearable Energy Harvesting: From body to battery 可穿戴能量收集:从身体到电池
M. Magno, D. Boyle
{"title":"Wearable Energy Harvesting: From body to battery","authors":"M. Magno, D. Boyle","doi":"10.1109/DTIS.2017.7930169","DOIUrl":"https://doi.org/10.1109/DTIS.2017.7930169","url":null,"abstract":"Energy Harvesting (EH) technologies provide promising solutions to overcome the short lifetime of wearable devices. In the last decade, EH has matured as a technology and found use in many application scenarios, such as smart grid and wireless sensor networks. Recently, advances have been made in miniaturizing EH devices to supply wearable devices by exploiting ambient energy in the form of motion, thermal gradients, light and electromagnetic radiation. However, harvesting energy from the body for powering wearable devices is more challenging due to strict constraints in terms of size, weight and cost. In this paper, we present a taxonomy of technologies, architectures and design trade-offs for efficient EH systems suitable for wearable devices. Additionally, we provide implementation details, including the conversion stages for kinetic and thermal EH, optimized for the human body. We quantify the energy that it is possible to harvest in real application scenarios, which is in the range of 200–700 mJ per day, depending the source, and result in up to 1.5 J per day if coupled. The design guidelines and experimental evaluations we present, with in-field measurement, will be of benefit to designers of future EH wearable systems.","PeriodicalId":328905,"journal":{"name":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121516675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 58
Integrated microelectromechanical systems in the More than Moore era 摩尔时代的集成微机电系统
J. Segura
{"title":"Integrated microelectromechanical systems in the More than Moore era","authors":"J. Segura","doi":"10.1109/DTIS.2017.7929870","DOIUrl":"https://doi.org/10.1109/DTIS.2017.7929870","url":null,"abstract":"The classical IC integration roadmap has followed the Moore law for decades bringing up an impressive transistor scaling evolution resulting in a profound transformation of our quotidian practices. Current trends face the development of integrating multi-domain magnitudes within current systems, demanding a wider diversification of the parameters being managed and enabling what has been named as the More than Moore paradigm. The monolithic integration of such diversity of magnitudes is a challenge that will enable low-cost, highly complex personal systems. A view for the specific microelectromechanical domain will be shared.","PeriodicalId":328905,"journal":{"name":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"161 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116182137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
NANOcom: A Mosaic Approach for nanoelectronic circuits design 纳米电子电路设计的镶嵌方法
Matteo Bollo, G. Santoro, U. Garlando, M. Zamboni
{"title":"NANOcom: A Mosaic Approach for nanoelectronic circuits design","authors":"Matteo Bollo, G. Santoro, U. Garlando, M. Zamboni","doi":"10.1109/DTIS.2017.7930161","DOIUrl":"https://doi.org/10.1109/DTIS.2017.7930161","url":null,"abstract":"In this paper we present a tool, NANOcom, specifically developed for the bottom-up design and formalization of electronic circuits with a regular, matrix-like, structure. NANOcom allows to easily describe any kind of circuits and technologies where neighboring logic elements are dynamically coupled. Logic elements and interconnections are placed on a three-dimensional grid. Each element is characterized with an RTL model that describes its logic behavior and how it communicates with neighboring elements. Starting from the grid layout and the model, NANOcom automatically creates a VHDL code describing the whole structure. NANOcom can be used to simulate both standard CMOS circuits, such as PLAs, and new emerging technologies, like NASICs (Nanoscale Application Specific Integrated Circuits), memristor-based circuits and field coupled technologies, such as Nanomagnet Logic (NML), Quantum dot Cellular Automata (QCA) and Molecular QCA.","PeriodicalId":328905,"journal":{"name":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"320 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122806327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Synthesis tool for design of complex polymorphic circuits 设计复杂多晶电路的综合工具
Adam Crha, R. Ruzicka, Václav Simek
{"title":"Synthesis tool for design of complex polymorphic circuits","authors":"Adam Crha, R. Ruzicka, Václav Simek","doi":"10.1109/DTIS.2017.7930179","DOIUrl":"https://doi.org/10.1109/DTIS.2017.7930179","url":null,"abstract":"This paper is dealing with research activities carried out in the domain of unconventional, polymorphic electronics. Main attention is focused on the logic synthesis aspects of complex polymorphic circuits. The introductory part elucidates a fundamental concept of polymorphic electronics and highlights its important properties. In addition, substantial advantages of this paradigm in comparison to conventional circuit design approach are discussed together with an identification of possible shortcomings. Main contribution of this paper is the proposal and implementation of a synthesis technique which makes it feasible to achieve an area-efficient results in case of complex polymorphic circuit involving hundreds of gates. Finally, accomplished experimental results and their analysis is provided.","PeriodicalId":328905,"journal":{"name":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129900448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A fully model-based approach to the design of the SEcube™ community web app 一个完全基于模型的方法来设计SEcube™社区web应用程序
S. Boßelmann, Dennis Kühn, T. Margaria
{"title":"A fully model-based approach to the design of the SEcube™ community web app","authors":"S. Boßelmann, Dennis Kühn, T. Margaria","doi":"10.1109/DTIS.2017.7930159","DOIUrl":"https://doi.org/10.1109/DTIS.2017.7930159","url":null,"abstract":"We present a model-driven approach to the creation of online community web apps that leverages the capabilities of the DIME model-driven development environment for web applications. Thereby we specifically focus the community-specific needs and structural elements and functionality of the online community around the SEcube™ project. Starting with only vague requirements, we applied a double scaffolding approach along the definition, structuring, and implementation of both the content as well as the features of the web application. We sketch how starting with a modeled but nearly plain prototype, we have continuously extended the feature set to establish a user-focused and dynamic solution for the community, and how this evolution influenced the ideas for building a specialized toolkit tailored towards the specific characteristics of community web apps.","PeriodicalId":328905,"journal":{"name":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126465710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Processor-based Symmetric Transparent BIST 基于处理器的对称透明BIST
I. Voyiatzis, C. Sgouropoulou, Giuseppe Airò Farulla
{"title":"Processor-based Symmetric Transparent BIST","authors":"I. Voyiatzis, C. Sgouropoulou, Giuseppe Airò Farulla","doi":"10.1109/DTIS.2017.7930173","DOIUrl":"https://doi.org/10.1109/DTIS.2017.7930173","url":null,"abstract":"Symmetric Transparent BIST schemes for RAM modules assure the preservation of the memory contents during periodic testing while at the same time skipping the signature prediction phase required in transparent BIST schemes, achieving considerable reduction in test time. In this work a processor based transparent approach for testing memories is presented. The proposed scheme uses the CPU to perform infield testing. Case study using the MIPS instruction set architecture is provided to demonstrate the applicability of the solution. In order to increase the effectiveness of the solution, a minor hardware modification is proposed that, without imposing any impact on the timing characteristics of the processor significantly decreases the testing time.","PeriodicalId":328905,"journal":{"name":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"2212 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130157449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On the generation of binary functions with low-overhead 低开销二进制函数的生成
I. Voyiatzis, C. Efstathiou
{"title":"On the generation of binary functions with low-overhead","authors":"I. Voyiatzis, C. Efstathiou","doi":"10.1109/DTIS.2017.7930167","DOIUrl":"https://doi.org/10.1109/DTIS.2017.7930167","url":null,"abstract":"In this work we present a low cost Boolean function generator based on the use of a decoder with tri-state outputs.","PeriodicalId":328905,"journal":{"name":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134579847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Formal analysis of bandwidth enhancement for high-performance active-input current mirror 高性能有源输入电流镜带宽增强的形式化分析
Mohan Julien, S. Bernard, F. Soulier, V. Kerzérho, G. Cathébras
{"title":"Formal analysis of bandwidth enhancement for high-performance active-input current mirror","authors":"Mohan Julien, S. Bernard, F. Soulier, V. Kerzérho, G. Cathébras","doi":"10.1109/DTIS.2017.7930162","DOIUrl":"https://doi.org/10.1109/DTIS.2017.7930162","url":null,"abstract":"High-performance CMOS current mirrors are used in a large variety of circuit as fundamental elements of analog design. As a consequence, several topologies have been proposed over the years to improve their performances. Among these solutions, the active input is mainly used to improve the speed of high-performance current mirrors. In this paper, we develop a complete formalism to evaluate the potential gain that can be expected using this topology. It allows designers to compute the optimal solution for their current source architecture. Then, comparative case studies are given to demonstrate the efficiency of our formalism to estimate capabilities and limits of the active-input current mirror topology.","PeriodicalId":328905,"journal":{"name":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123548460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Sound4All: Towards affordable large-scale hearing screening Sound4All:走向平价的大规模听力筛查
Nils Heitmann, Philipp H. Kindt, Thomas Rosner, K. Sikka, Amit Chirom, D. Kalyanasundaram, S. Chakraborty
{"title":"Sound4All: Towards affordable large-scale hearing screening","authors":"Nils Heitmann, Philipp H. Kindt, Thomas Rosner, K. Sikka, Amit Chirom, D. Kalyanasundaram, S. Chakraborty","doi":"10.1109/DTIS.2017.7930170","DOIUrl":"https://doi.org/10.1109/DTIS.2017.7930170","url":null,"abstract":"Hearing impairments are still prevalent, especially in rural areas of developing countries. Children in such areas have a high risk for hearing loss caused by malnutrition and inadequate medical facilities. In addition, many adults in urban areas are continuously exposed to high noise levels in their work environments (e.g., in factories or construction sites). However, the lack of regular screening often prevents timely interventions. This is mainly caused by the high prices of screening/testing equipment, which limit their availability especially in rural areas. Further, such equipment is currently designed to be used by specialists, which are often unavailable. In this paper, we outline techniques to develop low-cost screening devices, which are to be used by laypersons. They are intended to be utilized in the same way as clinical thermometers and blood pressure monitors are being used today. We propose possible solutions for realizing low-cost hearing screening equipment based on otoaccoustic emissions (OAE). We describe the principles as well as challenges of OAEs and propose solutions including multiple architectures. Our main goal is to design devices that are inexpensive, easy to use while still providing reliable hearing screening.","PeriodicalId":328905,"journal":{"name":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124273065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Evaluation of SRAM cell write margin metrics for lifetime monitoring of BTI-induced Vth drift 评估SRAM单元写裕度指标用于bti诱导的Vth漂移的终身监测
B. Alorda, G. Torrens
{"title":"Evaluation of SRAM cell write margin metrics for lifetime monitoring of BTI-induced Vth drift","authors":"B. Alorda, G. Torrens","doi":"10.1109/DTIS.2017.7930175","DOIUrl":"https://doi.org/10.1109/DTIS.2017.7930175","url":null,"abstract":"The Threshold voltage variability is increasing due to the process variability and reliability issues. SRAM cell stability dependence with threshold voltage is analyzed in order to extract reliability degradation due to BTI-induced Vth drift. The several write margin definitions are selected and their feasibility to be implemented in a threshold voltage built-in sensor is analyzed. The writability margins based on external cell nodes measurement have demonstrated best suitability for large memory arrays reducing the needs of hardware maintaining a good linearity for both high activity systems and long time storage.","PeriodicalId":328905,"journal":{"name":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125884902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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