评估SRAM单元写裕度指标用于bti诱导的Vth漂移的终身监测

B. Alorda, G. Torrens
{"title":"评估SRAM单元写裕度指标用于bti诱导的Vth漂移的终身监测","authors":"B. Alorda, G. Torrens","doi":"10.1109/DTIS.2017.7930175","DOIUrl":null,"url":null,"abstract":"The Threshold voltage variability is increasing due to the process variability and reliability issues. SRAM cell stability dependence with threshold voltage is analyzed in order to extract reliability degradation due to BTI-induced Vth drift. The several write margin definitions are selected and their feasibility to be implemented in a threshold voltage built-in sensor is analyzed. The writability margins based on external cell nodes measurement have demonstrated best suitability for large memory arrays reducing the needs of hardware maintaining a good linearity for both high activity systems and long time storage.","PeriodicalId":328905,"journal":{"name":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Evaluation of SRAM cell write margin metrics for lifetime monitoring of BTI-induced Vth drift\",\"authors\":\"B. Alorda, G. Torrens\",\"doi\":\"10.1109/DTIS.2017.7930175\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The Threshold voltage variability is increasing due to the process variability and reliability issues. SRAM cell stability dependence with threshold voltage is analyzed in order to extract reliability degradation due to BTI-induced Vth drift. The several write margin definitions are selected and their feasibility to be implemented in a threshold voltage built-in sensor is analyzed. The writability margins based on external cell nodes measurement have demonstrated best suitability for large memory arrays reducing the needs of hardware maintaining a good linearity for both high activity systems and long time storage.\",\"PeriodicalId\":328905,\"journal\":{\"name\":\"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-04-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DTIS.2017.7930175\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DTIS.2017.7930175","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

由于过程可变性和可靠性问题,阈值电压可变性正在增加。分析了SRAM单元稳定性与阈值电压的依赖关系,提取了由bti引起的Vth漂移引起的可靠性退化。选择了几种写余量定义,并分析了它们在阈值电压内置传感器中实现的可行性。基于外部单元节点测量的可写余量已证明最适合大型存储器阵列,减少了对硬件的需求,并为高活动系统和长时间存储保持了良好的线性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Evaluation of SRAM cell write margin metrics for lifetime monitoring of BTI-induced Vth drift
The Threshold voltage variability is increasing due to the process variability and reliability issues. SRAM cell stability dependence with threshold voltage is analyzed in order to extract reliability degradation due to BTI-induced Vth drift. The several write margin definitions are selected and their feasibility to be implemented in a threshold voltage built-in sensor is analyzed. The writability margins based on external cell nodes measurement have demonstrated best suitability for large memory arrays reducing the needs of hardware maintaining a good linearity for both high activity systems and long time storage.
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