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2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS)最新文献

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Anomalous Scaling of Parasitic Capacitance in FETs with a High-K Channel Material 高k通道材料fet寄生电容的异常缩放
2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2020-05-01 DOI: 10.1109/ICMTS48187.2020.9107901
A. Smink, Maurits J. de Jong, H. Hilgenkamp, W. G. van der Wiel, J. Schmitz
{"title":"Anomalous Scaling of Parasitic Capacitance in FETs with a High-K Channel Material","authors":"A. Smink, Maurits J. de Jong, H. Hilgenkamp, W. G. van der Wiel, J. Schmitz","doi":"10.1109/ICMTS48187.2020.9107901","DOIUrl":"https://doi.org/10.1109/ICMTS48187.2020.9107901","url":null,"abstract":"We investigate the operation of FETs with a high-K channel material, SrTiO3, (K=300). The transistors show low-leakage, high-capacitance operation with a sub-nm equivalent oxide thickness, in line with expectations. In depletion however, the gate-source capacitance appears to have an unusual 1/3power dependence on the device length and width. This awkward scaling behaviour is analyzed in detail in this paper and possible consequences for SrTiO3 devices and related 2D-material transistors are discussed. It is argued to relate to the high-permittivity channel. This high permittivity is further experimentally shown to result in strong short-channel effects in $10-mu mathrm{m} -$long FETs, in spite of the highly scaled equivalent oxide thickness, when the operation temperature is lowered to 4.2 K.","PeriodicalId":327379,"journal":{"name":"2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121642561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Experimental Set-Up For Novel Energy Efficient Charge-based Resistive RAM (RRAM) Switching 新型高能效电荷基电阻式RAM (RRAM)开关的实验装置
2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2020-05-01 DOI: 10.1109/ICMTS48187.2020.9107936
P. Trotti, G. Pillonet, G. Molas, S. Oukassi, E. Nowak
{"title":"Experimental Set-Up For Novel Energy Efficient Charge-based Resistive RAM (RRAM) Switching","authors":"P. Trotti, G. Pillonet, G. Molas, S. Oukassi, E. Nowak","doi":"10.1109/ICMTS48187.2020.9107936","DOIUrl":"https://doi.org/10.1109/ICMTS48187.2020.9107936","url":null,"abstract":"This work explores a new method to reduce the energy consumption during the writing of process-spread resistive-based memories (RRAM), based on setting an initial electrical charge into a writing capacitor rather than applying constant voltage over a fixed time. By connecting a charged capacitor (constant charge source, CQS) to a RRAM device, we benefit of a lower energy requirement for setting the memory cells, for a given success rate. We propose a RRAM set circuit model, where switching conditions were extrapolated from experimental data. We then benchmark our proposed writing procedure with respect to the constant voltage source (CVS) scheme. Finally, we give experimental proof of concept by realization of a circuit interface that integrates the CQS protocol and is connected to a RRAM load. Results support the fact that setting the initial charge is a better choice to efficiently control the variability of the filamentary process in RRAM.","PeriodicalId":327379,"journal":{"name":"2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130121363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Area-Efficient and Bias-Flexible Inline Monitoring Structure for Fast Characterization of RTN and Transistor Local Mismatch in Advanced Technologies 先进技术中快速表征RTN和晶体管局部失配的面积高效和偏置柔性在线监测结构
2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2020-05-01 DOI: 10.1109/ICMTS48187.2020.9107935
A. Jayakumar, N. Chan, L. Pirro, O. Zimmerhackl, M. Otto, T. Kleissner, J. Hoentschel
{"title":"Area-Efficient and Bias-Flexible Inline Monitoring Structure for Fast Characterization of RTN and Transistor Local Mismatch in Advanced Technologies","authors":"A. Jayakumar, N. Chan, L. Pirro, O. Zimmerhackl, M. Otto, T. Kleissner, J. Hoentschel","doi":"10.1109/ICMTS48187.2020.9107935","DOIUrl":"https://doi.org/10.1109/ICMTS48187.2020.9107935","url":null,"abstract":"An improved set of Scribe Line Monitors (SLMs) with high device densities have been designed for inline monitoring of Random Telegraph Noise (RTN) and transistor local mismatch. This infrastructure offers increased statistics from measurement on a single wafer with parallel Device Under Test (DUT) testing capability thereby having an efficient testing time. The characterization results from engineering silicon are presented in this paper.","PeriodicalId":327379,"journal":{"name":"2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125755023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Verification and Induction Method for Low Frequency Response Failure Modes in Acoustic MEMS 声学MEMS低频响应失效模式的验证与感应方法
2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2020-05-01 DOI: 10.1109/ICMTS48187.2020.9107925
Gergely Hantos, Desmulliez Marc P.Y.
{"title":"Verification and Induction Method for Low Frequency Response Failure Modes in Acoustic MEMS","authors":"Gergely Hantos, Desmulliez Marc P.Y.","doi":"10.1109/ICMTS48187.2020.9107925","DOIUrl":"https://doi.org/10.1109/ICMTS48187.2020.9107925","url":null,"abstract":"In this paper we present a novel verification and induction method for low frequency response failure modes in MEMS microphones. Response from the device is captured before and after the occurrence of a defect present on the diaphragm of the microphone and induced by focus ion beam machining. The deviation in the frequency response of the microphone shows a good agreement with analytical results.","PeriodicalId":327379,"journal":{"name":"2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122203297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Characterization of parametric mismatch attributable to plastic chip encapsulation 塑料芯片封装导致的参数失配特性
2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2020-05-01 DOI: 10.1109/ICMTS48187.2020.9107916
H. Tuinhout, A. Damian, A. Z. Duijnhoven
{"title":"Characterization of parametric mismatch attributable to plastic chip encapsulation","authors":"H. Tuinhout, A. Damian, A. Z. Duijnhoven","doi":"10.1109/ICMTS48187.2020.9107916","DOIUrl":"https://doi.org/10.1109/ICMTS48187.2020.9107916","url":null,"abstract":"This paper uses a high-spatial-resolution test structure and associated high-precision data analysis approach to characterize deterministic and random performance changes of semiconductor devices induced by local mechanical stress variations in plastic encapsulated chips. The results quantify substantial systematic effects caused by lead frame mounting and wire bonding as well as subtle random variability occurrences attributable to the spatial distribution of silica particles in the molding compound. The occurrence of these random silica particle effects is proven by comparing results of unprotected chips to results of those that received a chipcoat gel stress buffer layer prior to plastic chip encapsulation.","PeriodicalId":327379,"journal":{"name":"2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122726672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Investigation of Test Structures for the Characterization of Very Fast Electro Static Discharge Events 快速静电放电事件表征测试结构研究
2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2020-05-01 DOI: 10.1109/ICMTS48187.2020.9107924
M. Lauderdale, E. Onyegam, Scott Ruth, A. Gerdemann
{"title":"Investigation of Test Structures for the Characterization of Very Fast Electro Static Discharge Events","authors":"M. Lauderdale, E. Onyegam, Scott Ruth, A. Gerdemann","doi":"10.1109/ICMTS48187.2020.9107924","DOIUrl":"https://doi.org/10.1109/ICMTS48187.2020.9107924","url":null,"abstract":"New wafer technologies and chip design requirements are increasingly susceptible to damage from smaller Electro Static Discharge events (ESD). A new method is sought to evaluate ESD risk posed by processing equipment and the effectiveness of proposed upgrades. This paper proposes and investigates a packaged test structure designed to measure ESD events. The test chip would run in the place of production parts during equipment and package level process evaluations. A design is proposed, developed and preliminary test results demonstrating feasibility are shown.","PeriodicalId":327379,"journal":{"name":"2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129966355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Test Setup Optimization and Automation for Accurate Silicon Photonics Wafer Acceptance Production Tests 精确硅光子学晶圆验收生产测试的测试设置优化和自动化
2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2020-05-01 DOI: 10.1109/ICMTS48187.2020.9107907
C. Sia, T. L. Yap, Ashesh Sasidharan, J. Tan, Robin Chen, Jacobus Leo, Soon Leng Tan, Guo Chang Man
{"title":"Test Setup Optimization and Automation for Accurate Silicon Photonics Wafer Acceptance Production Tests","authors":"C. Sia, T. L. Yap, Ashesh Sasidharan, J. Tan, Robin Chen, Jacobus Leo, Soon Leng Tan, Guo Chang Man","doi":"10.1109/ICMTS48187.2020.9107907","DOIUrl":"https://doi.org/10.1109/ICMTS48187.2020.9107907","url":null,"abstract":"Implementing energy-efficient optical transceiver modules with silicon photonics (SiPh) and 3DIC technologies will help alleviate the increasing energy consumption for hyperscale data centers. To facilitate effective 3DIC heterogenous integration of these photonics integrated circuits for optical transceivers, high precision, repeatable and reliable SiPh wafer acceptance tests are essential and vital. This paper successfully demonstrated incident angle optimization for optical wafer tests as well as evaluation of a fully automatic SiPh wafer test architecture that is accurate and dependable, achieving excellent test correlations between passive and active devices designed with grating-couplers and edge couplers.","PeriodicalId":327379,"journal":{"name":"2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131584160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Calibration of CBCM Measurement Hardware CBCM测量硬件的校准
2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2020-05-01 DOI: 10.1109/ICMTS48187.2020.9107913
Brad Smith, E. Onyegam, D. Hall, B. Verzi
{"title":"Calibration of CBCM Measurement Hardware","authors":"Brad Smith, E. Onyegam, D. Hall, B. Verzi","doi":"10.1109/ICMTS48187.2020.9107913","DOIUrl":"https://doi.org/10.1109/ICMTS48187.2020.9107913","url":null,"abstract":"Charge-based capacitance (CBCM) measurements require precise measurement of AC currents. This work describes a test structure that produced periodic pulses of current to mimic a CBCM circuit. It was measured in both wafer form on a parametric test system and in package form on a functional test system. Average currents from 600 pA to $10 mu mathrm{A}$ at frequencies between 290 kHz and 2.6 GHz were measured on both systems. The parametric tester was shown to be capable of measuring AC currents across that entire range of currents and frequencies. The functional tester was capable at high frequencies, but showed measurement errors at lower currents, seemingly in agreement with its DC current measurement specifications. This technique could be used to validate the limits of any test hardware prior to designing an AC circuit.","PeriodicalId":327379,"journal":{"name":"2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134178893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Process Variation Estimation using An IDDQ Test and FlipFlop Retention Characteristics 使用IDDQ测试和触发器保持特性的过程变化估计
2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2020-05-01 DOI: 10.1109/ICMTS48187.2020.9107931
S. Nishizawa, Kazuhito Ito
{"title":"Process Variation Estimation using An IDDQ Test and FlipFlop Retention Characteristics","authors":"S. Nishizawa, Kazuhito Ito","doi":"10.1109/ICMTS48187.2020.9107931","DOIUrl":"https://doi.org/10.1109/ICMTS48187.2020.9107931","url":null,"abstract":"Extraction method of process variation is proposed. Process monitor circuits are widely used for the extraction of process variation, however adding special purpose circuit increase the silicon area. Usually, silicon chips are tested electrically and functionally after the fabrication. IDDQ test is an electrical test which measures leakage current and find the fault in the target chip. Scan-test is a functional test which inputs and measures the internal signal vector using scan-flip-flop. We propose to an extraction method of process variation utilizing IDDQ test and retention characteristics of scan-flip-flop. This method enables process variation extraction without any extra process monitor circuit. Test structures are implemented into silicon chips and result shows global variation shift is extracted as threshold voltage shift.","PeriodicalId":327379,"journal":{"name":"2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115568119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Drop-in test structure chip to visualize residual stress of Ru/Cu film grown by atomic layer deposition and supercritical fluid deposition 插入式测试结构芯片可以直观地显示原子层沉积和超临界流体沉积制备的Ru/Cu薄膜的残余应力
2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2020-05-01 DOI: 10.1109/ICMTS48187.2020.9107904
Naoto Usami, Etsuko Ota, A. Higo, T. Momose, Y. Mita
{"title":"Drop-in test structure chip to visualize residual stress of Ru/Cu film grown by atomic layer deposition and supercritical fluid deposition","authors":"Naoto Usami, Etsuko Ota, A. Higo, T. Momose, Y. Mita","doi":"10.1109/ICMTS48187.2020.9107904","DOIUrl":"https://doi.org/10.1109/ICMTS48187.2020.9107904","url":null,"abstract":"We propose a drop-in test structure chip to evaluate residual stress. The structure was applied to evaluate supercritical fluid deposition (SCFD) Cu film over atomic layer deposition (ALD) Ru/TiO 2 film. In an early development stage of such emerging technology, researchers make experiments with a small sample chip in a small chamber. Small chips make classical stress evaluation methods such as wafer curvature radius measurement inappropriate due to high chip stiffness. We propose to “dropin” altogether the sample chip and an additional tiny test chip equipped with free-standing MEMS test structure. The MEMS directly visualizes stress of the deposited material for both tensile and compressive ones. Researchers can continue the device fabrication process on the sample chip while obtaining stress information of the deposited layer by test structure chip. In this paper, in-plane rotating stress sensors were utilized for stress visualization. We proceeded SCFD with two different conditions. The results revealed that SCFD Cu film had tensile stress at the low-temperature condition and compressive stress at the hightemperature condition.","PeriodicalId":327379,"journal":{"name":"2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121724398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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