2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS)最新文献

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Experimental and simulation analysis of carrier lifetimes in GaAs/AlGaAs Avalanche Photo-Diodes GaAs/AlGaAs雪崩光电二极管载流子寿命的实验与仿真分析
2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2020-05-01 DOI: 10.1109/ICMTS48187.2020.9107920
F. Driussi, A. Pilotto, D. D. Belli, M. Antonelli, Fulvia Arfelli, Giorgio Biasiol, G. Cautero, R. Menk, C. Nichetti, L. Selmi, T. Steinhartova, P. Palestri
{"title":"Experimental and simulation analysis of carrier lifetimes in GaAs/AlGaAs Avalanche Photo-Diodes","authors":"F. Driussi, A. Pilotto, D. D. Belli, M. Antonelli, Fulvia Arfelli, Giorgio Biasiol, G. Cautero, R. Menk, C. Nichetti, L. Selmi, T. Steinhartova, P. Palestri","doi":"10.1109/ICMTS48187.2020.9107920","DOIUrl":"https://doi.org/10.1109/ICMTS48187.2020.9107920","url":null,"abstract":"Extensive experimental characterization and TCAD simulation analysis have been used to study the dark current in Avalanche Photo-Diodes (APDs). The comparison between the temperature dependence of measurements and simulations points out that SRH generation/recombination is responsible for the observed dark current. After the extraction of the carrier lifetimes in the GaAs layers, they have been used to predict the APD collection efficiency of the photo-generated currents under realistic operation conditions and as a function of the photogeneration position inside the absorption layer.","PeriodicalId":327379,"journal":{"name":"2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126354892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
ICMTS 2020 Cover Page ICMTS 2020封面
2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2020-05-01 DOI: 10.1109/icmts48187.2020.9107923
{"title":"ICMTS 2020 Cover Page","authors":"","doi":"10.1109/icmts48187.2020.9107923","DOIUrl":"https://doi.org/10.1109/icmts48187.2020.9107923","url":null,"abstract":"","PeriodicalId":327379,"journal":{"name":"2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126559443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Automated Generation, Fabrication and Measurement of Parametric Test Structures for Rapid Prototyping Using Optical Maskless Lithography 光学无掩模光刻快速成型参数化测试结构的自动生成、制造和测量
2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2020-05-01 DOI: 10.1109/ICMTS48187.2020.9107929
P. Sullivan, A. Tsiamis, M. Rondé, A. Walton, S. Smith, J. Terry
{"title":"Automated Generation, Fabrication and Measurement of Parametric Test Structures for Rapid Prototyping Using Optical Maskless Lithography","authors":"P. Sullivan, A. Tsiamis, M. Rondé, A. Walton, S. Smith, J. Terry","doi":"10.1109/ICMTS48187.2020.9107929","DOIUrl":"https://doi.org/10.1109/ICMTS48187.2020.9107929","url":null,"abstract":"This paper describes the use of open-source electronic design automation tools, which have been developed and adapted for maskless lithography, to enable automation of the design, layout and measurement of parametric test structures. Two test structures are presented as case studies for characterisation of microelectronic and micro-electromechanical systems technologies using electrical and profilometry measurements respectively.","PeriodicalId":327379,"journal":{"name":"2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123858358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Influence of series resistance on the experimental extraction of FinFET noise parameters 串联电阻对FinFET噪声参数实验提取的影响
2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2020-05-01 DOI: 10.1109/ICMTS48187.2020.9107908
A. Tataridou, G. Ghibaudo, C. Theodorou
{"title":"Influence of series resistance on the experimental extraction of FinFET noise parameters","authors":"A. Tataridou, G. Ghibaudo, C. Theodorou","doi":"10.1109/ICMTS48187.2020.9107908","DOIUrl":"https://doi.org/10.1109/ICMTS48187.2020.9107908","url":null,"abstract":"In this paper we demonstrate for the first time how the series resistance of an advanced CMOS device, such as the FinFET, can lead to an incorrect extraction of low-frequency noise parameters. In particular, the use of the carrier number fluctuations with correlated mobility fluctuations model is shown to be very sensitive to the transistor series resistance. We demonstrate how the classic fitting methods can lead to an underestimated value in the extraction of the mobility fluctuations factor $Omega$. Furthermore, we present an original method for suppressing this effect, by taking advantage of the series resistance immune Y-function.","PeriodicalId":327379,"journal":{"name":"2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS)","volume":"36 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120851804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Microheater isolation characterisation to aid the optimisation of a MEMS Leidenfrost engine 微加热器隔离特性,以帮助MEMS Leidenfrost发动机的优化
2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2020-04-09 DOI: 10.1109/ICMTS48187.2020.9107902
A. Buchoux, P. Agrawal, G. Wells, R. Ledesma-Aguilar, A. Walton, J. Terry, G. McHale, K. Sefiane, A. Stokes
{"title":"Microheater isolation characterisation to aid the optimisation of a MEMS Leidenfrost engine","authors":"A. Buchoux, P. Agrawal, G. Wells, R. Ledesma-Aguilar, A. Walton, J. Terry, G. McHale, K. Sefiane, A. Stokes","doi":"10.1109/ICMTS48187.2020.9107902","DOIUrl":"https://doi.org/10.1109/ICMTS48187.2020.9107902","url":null,"abstract":"This paper reports on the implementation of test structures to characterize the design of a microheater that facilitates localized heating to power a Leidenfrost micro-engines. The test structures are designed to characterize the effect on heat transfer of trenches etched into the silicon substrate. With no trench, the temperature difference is $triangle mathrm{T}=11.9$ oC. The temperature measured across the 412 $mu mathrm{m}$ deep “long” trench was 43.6 °C while it was 40.4 °C for the “short” trench. The results show that increasing the depth of the trench increases the temperature difference across the trench $(19.9{}^{circ}mathrm{C}$ increase for going from 73 $mu mathrm{m}$ to 412 $mu mathrm{m}$, for the “short” channel) while the length of the trench has a much less significant effect $(3.2{}^{circ}mathrm{C}$ increase from “short” to “long” trench, for a depth of 412 $mu mathrm{m})$. The test structure measurements agreed well with simulation results confirming the validity of using computer aided design as an integral part in the development of microheater designs.","PeriodicalId":327379,"journal":{"name":"2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128088535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Test Structure for Measuring the Selectivity in Vapour Etch Processes 气蚀过程中选择性测量的测试结构
2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2020-04-05 DOI: 10.1109/ICMTS48187.2020.9107934
M. Rondé, A. Walton, J. Terry
{"title":"Test Structure for Measuring the Selectivity in Vapour Etch Processes","authors":"M. Rondé, A. Walton, J. Terry","doi":"10.1109/ICMTS48187.2020.9107934","DOIUrl":"https://doi.org/10.1109/ICMTS48187.2020.9107934","url":null,"abstract":"Etch selectivity between layers is critical in the fabrication of microelectronics and microsystems. This is particularly true in the case of isotropic gas/vapour etching methods used to release free standing structures through the selective etching of sacrificial layers. Commonly used structural materials have been reported to be largely inert when exposed to a given vapour etchant, indicating high selectivity when measured against typical sacrificial layers. However, there is growing evidence that these structural layers are actually etched at an enhanced rate if they are located in the proximity of the sacrificial layer being removed. Hence, removal rates given in the literature that have resulted from measurements of layers that have been etched in isolation can no longer be trusted to characterize critical etch processes in device fabrication. In this paper, a test structure is reported that enables a far more accurate determination of the etch selectivity between sacrificial and structural materials. The method is demonstrated by a XeF2 vapour etch of a polysilicon sacrificial layer located above a silicon nitride structural layer. A dataset is presented for the polysilicon and silicon nitride layers, which shows a selectivity of 5:4.","PeriodicalId":327379,"journal":{"name":"2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115312902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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