IEEE/SEMI 1996 Advanced Semiconductor Manufacturing Conference and Workshop. Theme-Innovative Approaches to Growth in the Semiconductor Industry. ASMC 96 Proceedings最新文献

{"title":"Forming business partnerships with foreign corporations","authors":"L. Wagner","doi":"10.1109/ASMC.1996.558004","DOIUrl":"https://doi.org/10.1109/ASMC.1996.558004","url":null,"abstract":"Summary form only given, as follows. One of the fundamental trends of the 80's and 90's has been the growth of international business ties between companies. This is even more true in electronics in general and among semiconductor equipment companies in particular. Initially, these ties were mostly concentrated in the area of trade, as companies attempted to leverage domestic market acceptance abroad. Increasingly, these bonds are becoming more sophisticated, involving marketing and sales joint ventures, R&D cooperation projects, technology acquisition, etc. The drivers behind this trend are a desire to concentrate on core competencies, the need to amortize R&D investments over as large a customer base as possible and the increasing familiarity with the international environment. However, while the rewards of international cooperation can be high, many obstacles usually have to be overcome before success is at hand, and a significant number of projects are abandoned along the way because the partners no longer have enough in common to warrant continuing support. In the international realm, these obstacles-by definition-can be traced back to poor communication and cultural misunderstandings. Indeed, very subtle differences in assumptions about basic business practices can rapidly derail even the best laid plans. It is therefore critical to look at foreign cooperative projects with a different eye, to be cognizant of the challenges ahead and not to underestimate the demands placed on the available project management pool. Practical examples will be given of both positive and less satisfactory outcomes.","PeriodicalId":325204,"journal":{"name":"IEEE/SEMI 1996 Advanced Semiconductor Manufacturing Conference and Workshop. Theme-Innovative Approaches to Growth in the Semiconductor Industry. ASMC 96 Proceedings","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128503781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Improved color filter process for CCD and CMOS imagers","authors":"H. Miller","doi":"10.1109/ASMC.1996.557996","DOIUrl":"https://doi.org/10.1109/ASMC.1996.557996","url":null,"abstract":"Several different methods exist for converting monochromatic solid-state imagers into color. One of the first techniques was to rotate a color filter wheel in front of the sensor for each exposure. More recently, high-definition cameras align three different sensors and separate the color signals using dichroic filters mounted on a prism. Yet another method, known as \"on-chip\" color filters, applies a pattern of colored elements directly to the surface of the sensor. This type of filter is commonly produced by depositing successive layers and transferring a dye through a patterned photoresist. At Polaroid Corporation, color filters are produced in a unique, single-step photolithographic process by incorporating a dye directly into the resist prior to coating. The patterned photoresist and dye combination is then baked to stabilize the filter element against the next coating of colored photoresist. These color filters can often be sensitive to the high temperature bakes as well as other heat treatments found in the packaging process. Often the resist will reflow and discolor, thus reducing the resolution, sensitivity and production yield of the device. We are proposing a solution for eliminating or reducing the hard bakes between color by treating the filter elements with a silylating compound capable of cross-linking the photoresist by incorporating silicon into the polymeric chain. This process eliminates three baking steps and reduces the risk of reflowing and yellowing the resist as well as degrading the dye. Furthermore, the filters are sufficiently stabilized by silylation such that they can survive the high temperatures required for producing microlenses and completing the packaging process. A preferred silylation compound is hexamethylcyclotrisilazane (HMCTS). This same silylation compound can also be used to promote adhesion of the dyed photoresist layers and to replace a separate treatment by other commonly used silylation compounds such as hexamethyldisilazane (HMDS). This results in a process which is more robust and has a higher yield.","PeriodicalId":325204,"journal":{"name":"IEEE/SEMI 1996 Advanced Semiconductor Manufacturing Conference and Workshop. Theme-Innovative Approaches to Growth in the Semiconductor Industry. ASMC 96 Proceedings","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127671738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Using static capacity modeling techniques in semiconductor manufacturing","authors":"J. D. Witte","doi":"10.1109/ASMC.1996.557967","DOIUrl":"https://doi.org/10.1109/ASMC.1996.557967","url":null,"abstract":"In the capital intensive semiconductor industry, the ability to understand and communicate manufacturing capacity can mean the difference between profit and loss. Companies can make informed decisions on what, when, and how much equipment is needed to meet market demand only when their manufacturing capacity is understood. The use of static capacity modeling can provide a cost effective means for understanding and communicating manufacturing capability, while at the same time forming a foundation to build towards more sophisticated modeling techniques. Static capacity analysis can provide valid insight into some basic questions about manufacturing capability. In addition, static capacity modeling can simplify the data collection and validation effort, making capacity modeling an easier pill to swallow by front line manufacturing organizations that must maintain the model. This paper describes how Harris Semiconductor has implemented static capacity modeling analysis for strategic capital planning and enterprise wide production planning.","PeriodicalId":325204,"journal":{"name":"IEEE/SEMI 1996 Advanced Semiconductor Manufacturing Conference and Workshop. Theme-Innovative Approaches to Growth in the Semiconductor Industry. ASMC 96 Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131272399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Use of goal modeling and reliability engineering tools to accelerate availability improvement in new equipment development","authors":"A. J. King, H. Rojhantalab, D.A. Troness","doi":"10.1109/ASMC.1996.557969","DOIUrl":"https://doi.org/10.1109/ASMC.1996.557969","url":null,"abstract":"The challenge to improve capital equipment productivity in the semiconductor industry is made more acute for leading edge manufactures by the need to quickly bring new technologies on line and into cost-effective production. This paper describes the use of specific tools used to improve equipment availability in a process equipment development program at Intel. An availability model was developed to set goals and prioritize efforts. Using a set of known reliability tools, root cause solutions were found twice as fast as when no such tools were used. A practical guide to using these tools and integrating them into existing management structures is proposed.","PeriodicalId":325204,"journal":{"name":"IEEE/SEMI 1996 Advanced Semiconductor Manufacturing Conference and Workshop. Theme-Innovative Approaches to Growth in the Semiconductor Industry. ASMC 96 Proceedings","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128657119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"APC in the semiconductor industry, history and near term prognosis","authors":"G. Barna","doi":"10.1109/ASMC.1996.558084","DOIUrl":"https://doi.org/10.1109/ASMC.1996.558084","url":null,"abstract":"This paper presents an abridged history of Advanced Process Control (APC), including both Fault Detection and Classification (FDC) and Model Based Process Control (MBPC), both within TI and in the semiconductor industry. While TI was an early leader in univariate fault detection in processing tools, other manufacturers have by now implemented such methodologies. For MBPC, the MMST program gave TI a lead, but others are now following that path. For TI and the semiconductor industry as a whole, the current thrust is to develop and implement multivariate APC methods into the manufacturing operations. This paper describes the complexity of the execution of these tasks, and lists some of the available tools that are requisite for implementing these plans.","PeriodicalId":325204,"journal":{"name":"IEEE/SEMI 1996 Advanced Semiconductor Manufacturing Conference and Workshop. Theme-Innovative Approaches to Growth in the Semiconductor Industry. ASMC 96 Proceedings","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129037820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Non-linearity and randomness in a semiconductor wafer fab","authors":"S. Johal","doi":"10.1109/ASMC.1996.557961","DOIUrl":"https://doi.org/10.1109/ASMC.1996.557961","url":null,"abstract":"Conventional intuition of semiconductor wafer fab performance relies on assumptions of linear work flow and fixed (deterministic) behavior of the fab equipment's breakdown and capacity. This intuition is used to analyze fab capacity by using simple mathematical models in a \"spreadsheet\" fashion to obtain feasibility bounds on capacity (wafers out/unit time), cycle time (or lead time) and work-in-progress levels. However, assumptions of linearity and fixed behavior are not always valid, especially when strategic analysis needs to be done over long time horizons. This paper demonstrates the effects of such non-linearities and random (stochastic) behavior. This is done by modeling simple fab scenarios using advanced mathematical and discrete-event simulation tools. In particular, effects of a high degree of variance on equipment availability are investigated using serial representations of a manufacturing line. The impact of setup change-over times is also analyzed through random queuing scenarios in order to arrive at more accurate results of the line loading phenomenon. These results are then statistically analyzed to provide a contrast to conventional intuition.","PeriodicalId":325204,"journal":{"name":"IEEE/SEMI 1996 Advanced Semiconductor Manufacturing Conference and Workshop. Theme-Innovative Approaches to Growth in the Semiconductor Industry. ASMC 96 Proceedings","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115799747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Quintuple ramp up slope by implementing cross-functional, self-directed work teams","authors":"F.G. Boebel","doi":"10.1109/ASMC.1996.558108","DOIUrl":"https://doi.org/10.1109/ASMC.1996.558108","url":null,"abstract":"The 8-inch Advanced Semiconductor Line (ACL) in Essonnes-Corbeil, France is jointly run by Siemens and IBM with 16 MB DRAMs as the main product. Due to the increasing demand in 16 MB chips, it was decided to ramp up the line capacity by 70% between January and July 96. Although the tool installation happened as planned, the increase in daily going rate (DGR) was by a factor of 2 to 3 too small to meet the aggressive chips out plan for 96. A line analysis showed that the ramp up performance was mainly restricted by two reasons: First not reacting fast enough to line pinch points and second not synchronizing the \"4 partners\" (workforce, wafer flow, tool-set and process/business procedures) in an optimized way. To overcome those limitations, it was decided to install for each technology so-called productivity teams, which consist of a cross-functional selection of operators, technicians and engineers. The teams are responsible for problem localization as well as definition, installation and follow-ups of action plans, decision trees and check points on a daily basis as well as long term problem analysis. The empowerment of this low hierarchical workforce resulted in a much faster response to line problems and the cross-functional character of the teams propelled the synchronisation of the 4 partners. Two weeks after implementing the teams the line ramp up slope was increased by a factor of 5 and reached a peak value of DGR ramp up speed corresponding to 700 WSPW per month. 6 weeks after the introduction of productivity teams the DGR performance had recovered to the plan and is now (August 96) 3% above plan so that ACL expects to deliver significantly above the 96 plan.","PeriodicalId":325204,"journal":{"name":"IEEE/SEMI 1996 Advanced Semiconductor Manufacturing Conference and Workshop. Theme-Innovative Approaches to Growth in the Semiconductor Industry. ASMC 96 Proceedings","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125892508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A computer integrated manufacturing system for excursion management","authors":"D. N. Patel, D. Core, H.N. Nguyen, G. Martin, K. Mooney, G. Neri, D. Cresswell","doi":"10.1109/ASMC.1996.557965","DOIUrl":"https://doi.org/10.1109/ASMC.1996.557965","url":null,"abstract":"The current virtual factory excursion management system has proven itself in high volume manufacturing fabs and is flexible enough for continuous improvement. All system components described in this paper have successfully passed the ISO9002 surveillance. The material containment utility has allowed no escapes across the virtual factory. The Access DB is widely used to generate the health indicators of functional area or a factory. Automated reports help planning in meeting their output commitments by identifying material at risk in a factory. Periodic audit of this system will help in maintaining synergy across the virtual factory and help drive continuous line yield and die yield improvements in the virtual factory through shared learning.","PeriodicalId":325204,"journal":{"name":"IEEE/SEMI 1996 Advanced Semiconductor Manufacturing Conference and Workshop. Theme-Innovative Approaches to Growth in the Semiconductor Industry. ASMC 96 Proceedings","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127286784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Issues on the size and outline of killer defects and their influence on yield modeling","authors":"C. Hess, L. Weiland","doi":"10.1109/ASMC.1996.558102","DOIUrl":"https://doi.org/10.1109/ASMC.1996.558102","url":null,"abstract":"Yield prediction models and critical area calculations based on on defects modeled as circular disks. But, the observation of real defects provides mostly irregular defect outlines. For this reason, we investigate the influence of real defect outlines on determining defect size distributions for yield prediction. To collect data on defects, checkerboard test structures were manufactured that enable a precise localization of defects inside large chip areas. Furthermore, we introduce a methodology to calculate a general defect size distribution that includes variety of real defect outlines. So, this realistic size distribution will be compared to defect size distributions based on known yield models to describe defect outlines.","PeriodicalId":325204,"journal":{"name":"IEEE/SEMI 1996 Advanced Semiconductor Manufacturing Conference and Workshop. Theme-Innovative Approaches to Growth in the Semiconductor Industry. ASMC 96 Proceedings","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133346365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Production worthy 0.25 /spl mu/m polycide gate etch system","authors":"K. Olson, L. Mcculloch, J. Liu","doi":"10.1109/ASMC.1996.558029","DOIUrl":"https://doi.org/10.1109/ASMC.1996.558029","url":null,"abstract":"Gate geometry decreases create an increased demand for Tungsten polycide use due to its outstanding thermal stability and low resistivity. Tungsten polycide (W-Si) on polysilicon stacked gate is defined by the process of sequential etch of the two layers. This process requires high etch selectivities between W-Si and polysilicon, and between polysilicon and oxide; good etch uniformity for both layers; and vertical profile without undercut and notching, in addition to the polysilicon-only gate etch. As the industry moves toward mainstream production of smaller and smaller feature sizes the importance of consistent and stable etching results are only matched by the importance of machine reliability. In the Tegal 6510 HRe/sup -/ high density etcher, a demonstration of 0.25 /spl mu/m thin stack silicide technology was performed. Process stability and equipment reliability were evaluated using extensive passive data collection and IRONMAN methodology respectively.","PeriodicalId":325204,"journal":{"name":"IEEE/SEMI 1996 Advanced Semiconductor Manufacturing Conference and Workshop. Theme-Innovative Approaches to Growth in the Semiconductor Industry. ASMC 96 Proceedings","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132555673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}