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IEEE SoutheastCon, 2004. Proceedings.最新文献

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A Cycle Reducing Synchronous Logic Simulation 减少周期的同步逻辑仿真
IEEE SoutheastCon, 2004. Proceedings. Pub Date : 2004-03-26 DOI: 10.1109/SECON.2004.1287893
Jinsheng Xu, M. Chung
{"title":"A Cycle Reducing Synchronous Logic Simulation","authors":"Jinsheng Xu, M. Chung","doi":"10.1109/SECON.2004.1287893","DOIUrl":"https://doi.org/10.1109/SECON.2004.1287893","url":null,"abstract":"Parallel logic simulation is an important method for verifying the correctness of complex VLSI system designs. Synchronous simulation technique has low overhead but has poor load balancing and frequent synchronization cost. We derive a performance evaluation formula for the synchronous simulation. The formula considers factors including load balancing, the ratio between computation and communication and number of simulation cycles. The formula reveals that for simulations with very fine computation granularity, the reduction in simulation cycles is one of the most important keys to improve the performance. We propose an optimistic synchronous algorithm that is targeted to reduce the number of synchronization steps. The experimental results on ISCAS89 and ISCAS85 circuits show that the proposed algorithm performs significantly better than synchronous simulation. For non-unit delay models, the proposed algorithm performs almost as good as unit delay models.","PeriodicalId":324953,"journal":{"name":"IEEE SoutheastCon, 2004. Proceedings.","volume":"25 48","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132742895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Software Architecture for Simulated Human-Human Conversation with User Intervention 具有用户干预的模拟人机对话的软件体系结构
IEEE SoutheastCon, 2004. Proceedings. Pub Date : 2004-03-26 DOI: 10.1109/SECON.2004.1287897
N. Green
{"title":"A Software Architecture for Simulated Human-Human Conversation with User Intervention","authors":"N. Green","doi":"10.1109/SECON.2004.1287897","DOIUrl":"https://doi.org/10.1109/SECON.2004.1287897","url":null,"abstract":"We present the high-level design of a prototype AIbased interactive system that simulates conversation between two animated virtual characters. The conversational choices made by each character are influenced by dynamic models of each virtual participant's mental state. Also, the choices made by one character, the user's Conversational Avatar, are at certain times under user control. This style of simulated conversation with user intervention is applicable to a range of potential applications in education and entertainment. Our current application is a training system for coaching caregivers on having social conversations with persons with Alzheimer's Disease.","PeriodicalId":324953,"journal":{"name":"IEEE SoutheastCon, 2004. Proceedings.","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128502427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Cache Memory Simulators: A Comparative Study 缓存存储器模拟器:比较研究
IEEE SoutheastCon, 2004. Proceedings. Pub Date : 2004-03-26 DOI: 10.1109/SECON.2004.1287907
Xiaohong Yuan, S. Aboughalyoun, D. Williamson, A. Nixon
{"title":"Cache Memory Simulators: A Comparative Study","authors":"Xiaohong Yuan, S. Aboughalyoun, D. Williamson, A. Nixon","doi":"10.1109/SECON.2004.1287907","DOIUrl":"https://doi.org/10.1109/SECON.2004.1287907","url":null,"abstract":"Many computer architecture and organization instructors are turning to simulators with visualization as teaching aids. Many simulators have already been developed and made freely available on the Internet. It is beneficial to document and organize these simulators to all instructors of computer architecture and organization courses to take full advantage of this time-saving resource conveniently. This paper describes and analyzes three cache memory simulators. These cache memory simulators can be used with the popular computer architecture and organization textbooks. Our document of these cache memory simulators and comparative evaluation of their usability may provide computer architecture instructors with insight in selecting appropriate cache memory simulators to satisfy their pedagogical needs.","PeriodicalId":324953,"journal":{"name":"IEEE SoutheastCon, 2004. Proceedings.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123359173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Noise Optimization for CMOS RF Balanced Mixers CMOS射频平衡混频器的噪声优化
IEEE SoutheastCon, 2004. Proceedings. Pub Date : 2004-03-26 DOI: 10.1109/SECON.2004.1287924
J. Long, R. Weber
{"title":"Noise Optimization for CMOS RF Balanced Mixers","authors":"J. Long, R. Weber","doi":"10.1109/SECON.2004.1287924","DOIUrl":"https://doi.org/10.1109/SECON.2004.1287924","url":null,"abstract":"Noise features of balanced CMOS RF direct downconversion mixer are examined and analyzed in this paper. Optimal port matching circuit architectures are proposed for RF, LO and output ports to improve the mixer's performance. Based on the analysis, both a singlebalanced and a double-balanced direct down-conversion mixers are designed using a 0.18μm CMOS process, with a 1.2V power supply. With a 2.41GHz RF signal of ¿30dBm driven by a 2.4GHz LO signal of ¿10dBm, both mixers have shown good performance in noise figure and conversion gain. The double-balanced one is in process of fabrication through MOSIS.","PeriodicalId":324953,"journal":{"name":"IEEE SoutheastCon, 2004. Proceedings.","volume":"187 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116617955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The LoSS Technique for Detecting New Denial of Service Attacks 检测新型拒绝服务攻击的损失技术
IEEE SoutheastCon, 2004. Proceedings. Pub Date : 2004-03-26 DOI: 10.1109/SECON.2004.1287935
W. Allen, G. Marin
{"title":"The LoSS Technique for Detecting New Denial of Service Attacks","authors":"W. Allen, G. Marin","doi":"10.1109/SECON.2004.1287935","DOIUrl":"https://doi.org/10.1109/SECON.2004.1287935","url":null,"abstract":"We present a new technique for detecting the possible presence of certain Denial-of-Service attacks in network traffic. The effectiveness of the technique is demonstrated in experiments against 23 attacks in three different traffic backgrounds. Even though some attacks persist for only 2-4 seconds, results show detection rates up to 84%. Results also show that (for these data) the technique can be tuned to eliminate false alarms. These results are especially favorable given the technique's objective of detecting new (previously unseen) attacks without a template of the background traffic.","PeriodicalId":324953,"journal":{"name":"IEEE SoutheastCon, 2004. Proceedings.","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122442532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
An Automated Approach in Reverse Engineering Java Applications Using Petri Nets 使用Petri网逆向工程Java应用程序的自动化方法
IEEE SoutheastCon, 2004. Proceedings. Pub Date : 2004-03-26 DOI: 10.1109/SECON.2004.1287903
Jared Fuhs, James Cannady
{"title":"An Automated Approach in Reverse Engineering Java Applications Using Petri Nets","authors":"Jared Fuhs, James Cannady","doi":"10.1109/SECON.2004.1287903","DOIUrl":"https://doi.org/10.1109/SECON.2004.1287903","url":null,"abstract":"In this paper, we propose a new approach for reverse engineering Java applications into Petri Net structures. Our approach rests on utilizing the foundations of Petri Nets as a means of uncovering certain attributes of interests. Petri Nets offers techniques of predicting path execution, flow complexity, dead paths, and resource utilization. The conclusion of this work will provide the strengths and weaknesses of using this approach along with future recommendations of research.","PeriodicalId":324953,"journal":{"name":"IEEE SoutheastCon, 2004. Proceedings.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115848644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A Review of Adaptive Neural Networks 自适应神经网络研究进展
IEEE SoutheastCon, 2004. Proceedings. Pub Date : 2004-03-26 DOI: 10.1109/SECON.2004.1287896
R. Palnitkar, J. Cannady
{"title":"A Review of Adaptive Neural Networks","authors":"R. Palnitkar, J. Cannady","doi":"10.1109/SECON.2004.1287896","DOIUrl":"https://doi.org/10.1109/SECON.2004.1287896","url":null,"abstract":"Artificial neural networks are inspired from their biological counterparts. Adaptation is one of the most important features of both types of networks. Adaptive artificial neural networks are a class of networks used in dynamic environments. They are characterized by online learning. A number of techniques are used to provide adaptability to neural networks: adaptation by weight modification, by neuronal property modification, and by network structure modification. A brief review of various types of implementations is provided.","PeriodicalId":324953,"journal":{"name":"IEEE SoutheastCon, 2004. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130878983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Effects of Varying Parameters in Asymmetric AdaBoost on the Accuracy of a Cascade Audio Classifier 非对称AdaBoost中参数变化对级联音频分类器精度的影响
IEEE SoutheastCon, 2004. Proceedings. Pub Date : 2004-03-26 DOI: 10.1109/SECON.2004.1287913
M. Healy, S. Ravindran, D.V. Anderson
{"title":"Effects of Varying Parameters in Asymmetric AdaBoost on the Accuracy of a Cascade Audio Classifier","authors":"M. Healy, S. Ravindran, D.V. Anderson","doi":"10.1109/SECON.2004.1287913","DOIUrl":"https://doi.org/10.1109/SECON.2004.1287913","url":null,"abstract":"Previous work has been done demonstrating that the asymmetric AdaBoost algorithm could be successfully used to design a binary classifier that is a cascade of simple classifiers. We use the algorithm to design an audio classifier and study the effect of changing the length of the cascade and the weighting at each stage on the accuracy of the classifier. Results for a four-class audio classification problem are presented.","PeriodicalId":324953,"journal":{"name":"IEEE SoutheastCon, 2004. Proceedings.","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130480780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
S-Parameters for Three and Four Cascaded Two-Ports 3和4级联双端口s参数
IEEE SoutheastCon, 2004. Proceedings. Pub Date : 2004-03-26 DOI: 10.1109/SECON.2004.1287952
M. Sadiku, C. Akujuobi
{"title":"S-Parameters for Three and Four Cascaded Two-Ports","authors":"M. Sadiku, C. Akujuobi","doi":"10.1109/SECON.2004.1287952","DOIUrl":"https://doi.org/10.1109/SECON.2004.1287952","url":null,"abstract":"This paper presents explicit formulas for the resultant Sparameters for cascaded three and four two-ports in terms of the S-parameters of the individual two-ports. The formulas are derived in two ways (multiplication of the T-parameters and signal flow graph) giving the same result. They are also confirmed by simulation.","PeriodicalId":324953,"journal":{"name":"IEEE SoutheastCon, 2004. Proceedings.","volume":"139 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134203954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Span Space Data Structures for Multithreaded Isosurfacing 多线程等面处理的跨空间数据结构
IEEE SoutheastCon, 2004. Proceedings. Pub Date : 2004-03-26 DOI: 10.1109/SECON.2004.1287933
Huijuan Zhang, Timothy S Newman
{"title":"Span Space Data Structures for Multithreaded Isosurfacing","authors":"Huijuan Zhang, Timothy S Newman","doi":"10.1109/SECON.2004.1287933","DOIUrl":"https://doi.org/10.1109/SECON.2004.1287933","url":null,"abstract":"A data structure that can enable efficient isosurface extraction on desktop (single- and dual-CPU) computers is introduced. The data structure enables avoidance of unnecessary processing in the isosurface extraction while consuming little memory. Incorporation of the data structure into multithreading strategies that allow exploitation of slack computational processing resources, especially on hyperthreaded CPUs, is also described.","PeriodicalId":324953,"journal":{"name":"IEEE SoutheastCon, 2004. Proceedings.","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116101599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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