2014 IX Southern Conference on Programmable Logic (SPL)最新文献

Hardware-accelerated spike train generation for neuromorphic image and video processing 神经形态图像和视频处理的硬件加速尖峰序列生成

2014 IX Southern Conference on Programmable Logic (SPL) Pub Date : 2014-11-01 DOI: 10.1109/SPL.2014.7002206

T. Iakymchuk, A. Rosado-Muñoz, M. Bataller-Mompeán, J. Guerrero-Martinez, J. V. Francés-Víllora, M. Węgrzyn, M. Adamski

引用次数: 6

Hardware design of an NTT-based polynomial multiplier 基于ntt的多项式乘法器的硬件设计

2014 IX Southern Conference on Programmable Logic (SPL) Pub Date : 2014-11-01 DOI: 10.1109/SPL.2014.7002209

Claudia Patricia Renteria-Mejia, Jaime Velasco-Medina

引用次数: 12

An image descriptors extraction hardware-architecture inspired on Human Retina 一种基于人眼视网膜的图像描述符提取硬件架构

2014 IX Southern Conference on Programmable Logic (SPL) Pub Date : 2014-11-01 DOI: 10.1109/SPL.2014.7002205

E. D. Bello, P. Salvadeo

引用次数: 7

Validation of an on-chip watchdog for embedded systems exposed to radiation and conducted EMI 对暴露于辐射和传导EMI的嵌入式系统的片上看门狗的验证

2014 IX Southern Conference on Programmable Logic (SPL) Pub Date : 2014-11-01 DOI: 10.1109/SPL.2014.7002212

C. Oliveira, J. Benfica, L. B. Bolzani Poehls, F. Vargas, J. Lipovetzky, A. Lutenberg, E. Gatti, F. Hernandez

{"title":"Validation of an on-chip watchdog for embedded systems exposed to radiation and conducted EMI","authors":"C. Oliveira, J. Benfica, L. B. Bolzani Poehls, F. Vargas, J. Lipovetzky, A. Lutenberg, E. Gatti, F. Hernandez","doi":"10.1109/SPL.2014.7002212","DOIUrl":"https://doi.org/10.1109/SPL.2014.7002212","url":null,"abstract":"Due to stringent constraints such as battery-powered, high-speed, low-voltage power supply and noise-exposed operation, safety-critical real-time embedded systems are often subject to transient faults originated from a large spectrum of noisy sources; among them, conducted Electromagnetic Interference (EMI) and radiation. As the major consequence, the system's reliability degrades. In this paper, we present the most recent results involving the validation analysis of a hardware-based intellectual property (IP) core, namely Real-Time Operating System - Guardian (RTOS-G). This is an on-chip watchdog that monitors the RTOS' activity in order to detect faults that corrupt tasks' execution flow in embedded systems running preemptive RTOS. Experimental results based on the Plasma processor IP core running different test programs that exploit several RTOS resources have been developed. During test execution, the proposed system was aged by means of total ionizing dose (TID) radiation and then, exposed to conducted EMI according to the international standard IEC 61.000-4-29 (voltage dips on the VDD power pins). The obtained results demonstrate the proposed approach provides higher fault coverage and reduced fault latency when compared to the native (software) fault detection mechanisms embedded in the kernel of the RTOS.","PeriodicalId":320882,"journal":{"name":"2014 IX Southern Conference on Programmable Logic (SPL)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126197738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Educating hardware design — From boolean equations to massively parallel computing systems 教育硬件设计。从布尔方程到大规模并行计算系统

2014 IX Southern Conference on Programmable Logic (SPL) Pub Date : 2014-11-01 DOI: 10.1109/SPL.2014.7002216

Oliver Knodel, M. Zabel, Patrick Lehmann, R. Spallek

{"title":"Educating hardware design — From boolean equations to massively parallel computing systems","authors":"Oliver Knodel, M. Zabel, Patrick Lehmann, R. Spallek","doi":"10.1109/SPL.2014.7002216","DOIUrl":"https://doi.org/10.1109/SPL.2014.7002216","url":null,"abstract":"The future of hardware development lies in massively parallel hardware architectures as used in embedded as well as high-performance systems, for instance streaming-based, realtime and database applications. Especially field-programmable gate arrays provide a platform for the rapid development of integrated circuits and the accompanied software. For reasons of energy efficiency, it is increasingly important to tailor hardware directly to the application. As such systems are very complex, the training of engineers has to start early. Furthermore, the usual curricula in computer science and electrical engineering teach only basic skills. In this paper we present lectures and especially practical FPGA design courses for bachelor and master students. We introduce a selection of individual projects, which were realized by students in practical courses. With examples from final bachelor projects and master theses we demonstrate the quality of education and its integration into current research. We describe possible improvements of labs, such as automated test benches and a remote FPGA laboratory for advanced courses.","PeriodicalId":320882,"journal":{"name":"2014 IX Southern Conference on Programmable Logic (SPL)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127413833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

The Hamiltonian-based odd-even routing method for 3D Networks-on-Chip 基于哈密顿的三维片上网络奇偶路由方法

2014 IX Southern Conference on Programmable Logic (SPL) Pub Date : 2014-11-01 DOI: 10.1109/SPL.2014.7002203

Poona Bahrebar, D. Stroobandt

引用次数: 2

Wavelet hardware processing unit for transient signal detection 用于瞬态信号检测的小波硬件处理单元

2014 IX Southern Conference on Programmable Logic (SPL) Pub Date : 2014-11-01 DOI: 10.1109/SPL.2014.7002200

Juan Marcos Macchi Konrad, L. de Pasquale, Miguel Angel Banchieri, Guillermo H. Reggiani, R. Cayssials, E. Ferro

引用次数: 1

miniFPGA: An educational app for teaching partitioning, placemnent and routing on Andriod devices miniFPGA: android设备上用于教学分区、放置和路由的教育应用程序

2014 IX Southern Conference on Programmable Logic (SPL) Pub Date : 2014-11-01 DOI: 10.1109/SPL.2014.7002217

Adrian Moreno-Villalón, Ángel Guerra-Martín, E. Boemo

引用次数: 1

FPGA implementation of a FEC decoding subsystem for a DVB-S2 receiver DVB-S2接收机FEC解码子系统的FPGA实现

2014 IX Southern Conference on Programmable Logic (SPL) Pub Date : 2014-11-01 DOI: 10.1109/SPL.2014.7002218

Denise C. Alves, C. G. Chaves, E. R. De Lima, Gabriel S. da Silva, A. F. R. Queiroz

引用次数: 3

Components for Coverage-Driven Verification of floating-point units 用于覆盖驱动的浮点单元验证的组件

2014 IX Southern Conference on Programmable Logic (SPL) Pub Date : 2014-11-01 DOI: 10.1109/SPL.2014.7002208

O. Goni, E. Todorovich

引用次数: 3